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参数资料
| 型号： | M38039GCHWG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封装： | 6 X 6 MM, 0.65 PITCH, FLGA-64 |
| 文件页数： | 85/103页 |
| 文件大小： | 1412K |
| 代理商： | M38039GCHWG |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 82 of 100
3803 Group (Spec.H QzROM version)
Notes on Interrupts
1. Change of relevant register settings
When the setting of the following registers or bits is changed, the
interrupt request bit may be set to “1”. When not requiring the
interrupt occurrence synchronized with these setting, take the
following sequence.
Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
Set the above listed registers or bits as the following sequence.
Fig 80. Sequence of changing relevant register
<Reason>
2. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt
request bit of an interrupt request register immediately after this
bit is set to “0”, execute one or more instructions before
executing the BBC or BBS instruction.
Fig 81. Sequence of check of interrupt request bit
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit of an interrupt request register is cleared to
“0”, the value of the interrupt request bit before being cleared to
“0” is read.
Notes on 8-bit Timer (timer 1, 2, X, Y)
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
When switching the count source by the timer 12, X and Y
count source selection bits, the value of timer count is altered
in unconsiderable amount owing to generating of thin pulses in
the count input signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
Set the double-function port of the CNTR0/CNTR1 pin and
port P54/P55 to output in the pulse output mode.
Set the double-function port of CNTR0/CNTR1 pin and port
P54/P55 to input in the event counter mode and the pulse width
measurement mode.
Set the interrupt edge select bit (active edge switch bit)
or the interrupt (source) select bit to “1”.
NOP (one or more instructions)
Set the corresponding interrupt enable bit to “0” (disabled).
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
Set the corresponding interrupt enable bit to “1” (enabled).
NOP (one or more instructions)
Clear the interrupt request bit to “0” (no interrupt issued)
Execute the BBC or BBS instruction
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