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参数资料
型号： M38039GCHWG
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封装： 6 X 6 MM, 0.65 PITCH, FLGA-64
文件页数： 99/103页
文件大小： 1412K
代理商： M38039GCHWG
REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 95 of 100
3803 Group (Spec.H QzROM version)
NOTES:
1. When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
Table 19
Timing requirements (2)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
tC(SCLK1)
tC(SCLK3)
Serial I/O1, serial I/O3
clock input cycle time(1)
4.5
≤ VCC ≤ 5.5 V
250
ns
4.0
≤ VCC < 4.5 V
320
2.7
≤ VCC < 4.0 V
500
2.2
≤ VCC < 2.7 V
1000
2.0
≤ VCC < 2.2 V
2000
tWH(SCLK1)
tWH(SCLK3)
Serial I/O1, serial I/O3
clock input “H” pulse width(1)
4.5
≤ VCC ≤ 5.5 V
120
ns
4.0
≤ VCC < 4.5 V
150
2.7
≤ VCC < 4.0 V
240
2.2
≤ VCC < 2.7 V
480
2.0
≤ VCC < 2.2 V
950
tWL(SCLK1)
tWL(SCLK3)
Serial I/O1, serial I/O3
clock input “L” pulse width(1)
4.5
≤ VCC ≤ 5.5 V
120
ns
4.0
≤ VCC < 4.5 V
150
2.7
≤ VCC < 4.0 V
240
2.2
≤ VCC < 2.7 V
480
2.0
≤ VCC < 2.2 V
950
tsu(RxD1-SCLK1)
tsu(RxD3-SCLK3)
Serial I/O1, serial I/O3
clock input setup time
4.5
≤ VCC ≤ 5.5 V
70
ns
4.0
≤ VCC < 4.5 V
90
2.7
≤ VCC < 4.0 V
100
2.2
≤ VCC < 2.7 V
200
2.0
≤ VCC < 2.2 V
400
th(SCLK1-RxD1)
th(SCLK3-RxD3)
Serial I/O1, serial I/O3
clock input hold time
4.5
≤ VCC ≤ 5.5 V
32
ns
4.0
≤ VCC < 4.5 V
40
2.7
≤ VCC < 4.0 V
50
2.2
≤ VCC < 2.7 V
100
2.0
≤ VCC < 2.2 V
200
tC(SCLK2)Serial I/O2
clock input cycle time
4.5
≤ VCC ≤ 5.5 V
500
ns
4.0
≤ VCC < 4.5 V
650
2.7
≤ VCC < 4.0 V
1000
2.2
≤ VCC < 2.7 V
2000
2.0
≤ VCC < 2.2 V
4000
tWH(SCLK2)Serial I/O2
clock input “H” pulse width
4.5
≤ VCC ≤ 5.5 V
200
ns
4.0
≤ VCC < 4.5 V
260
2.7
≤ VCC < 4.0 V
400
2.2
≤ VCC < 2.7 V
950
2.0
≤ VCC < 2.2 V
2000
tWL(SCLK2)Serial I/O2
clock input “L” pulse width
4.5
≤ VCC ≤ 5.5 V
200
ns
4.0
≤ VCC < 4.5 V
260
2.7
≤ VCC < 4.0 V
400
2.2
≤ VCC < 2.7 V
950
2.0
≤ VCC < 2.2 V
2000
tsu(SIN2-SCLK2)Serial I/O2
clock input setup time
4.5
≤ VCC ≤ 5.5 V
100
ns
4.0
≤ VCC < 4.5 V
130
2.7
≤ VCC < 4.0 V
200
2.2
≤ VCC < 2.7 V
400
2.0
≤ VCC < 2.2 V
800
th(SCLK2-SIN2)Serial I/O2
clock input hold time
4.5
≤ VCC ≤ 5.5 V
100
ns
4.0
≤ VCC < 4.5 V
130
2.7
≤ VCC < 4.0 V
150
2.2
≤ VCC < 2.7 V
300
2.0
≤ VCC < 2.2 V
600
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