参数资料
型号: M38748EAF-XXXFS
厂商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 单芯片8位CMOS微机
文件页数: 42/92页
文件大小: 1292K
代理商: M38748EAF-XXXFS
42
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 36 Structure of serial I/O3 control register 3
G
Serial I/O3 Operation
An internal or external synchronous clock can be selected as the
serial transfer synchronous clock by the serial I/O3 synchronous
clock selection bits of the serial I/O3 control register 1.
Since the internal synchronous clock has its own built-in divider, 8
types of clocks can be selected by the serial I/O3 internal synchro-
nous clock selection bits of the serial I/O3 control register 3.
Either I/O port or handshake I/O signal function can be selected
for the P8
5
/S
RDY3
, P8
6
/S
BUSY3
, and P8
7
/S
STB3
pins by the serial
I/O3 synchronous clock selection bits (P8
7
/S
STB3
pin control bits)
of the serial I/O3 control register 1 or the P8
5
/S
RDY3
P8
6
/S
BUSY3
pin control bits of the serial I/O3 control register 2.
CMOS output or N-channel open-drain output can be selected for
the S
CLK3
and S
OUT3
output pins by the P8
2
/S
OUT3
P8
4
/S
CLK3
P-
channel output disable bit of the serial I/O3 control register 2.
The S
OUT3
output control bit of the serial I/O3 control register 2
can be used to select the status of the S
OUT3
pin when serial data
is not transferred; either output active or high-impedance. How-
ever, when selecting an external synchronous clock, the S
OUT3
pin can go to the high-impedance status by setting the S
OUT3
out-
put control bit to “1” when S
CLK3
input is at “H” after transfer
completion. When the next serial transfer begins and S
CLK3
goes
to “L”, the S
OUT3
output control bit is automatically reset to “0” and
goes to an output active status.
Regardless of selecting an internal or external synchronous clock,
the serial transfer has both a full duplex mode as well as a trans-
mit-only mode. These modes are set by the transfer mode
selection bit of serial I/O3 control register 1.
LSB first or MSB first can be selected for the input/output order of
the serial transfer bit string by the serial I/O3 transfer direction se-
lection bit of serial I/O3 control register 1.
In order to use serial I/O3, the following process must be followed
after all of the above set have been completed: First, select any
one of 8-bit serial I/O, arbitrary bit serial I/O, or auto-transfer serial
I/O by setting the serial transfer selection bits of the serial I/O3
control register 1. Then, enable the serial I/O by setting the serial
I/O initialization bit of the serial I/O3 control register 1 to “1”.
Whether using an internal or external synchronous clock, set the
serial I/O initialization bit to “0” when terminating a serial transfer
during the transmission.
b7
b0
Serial I/O3 control register 3
(SIO3CON3 (SC33) : address 0016
16
)
Serial I/O3 internal synchronous clock selection bits
000: f(X
IN
)/4 or f(X
CIN
)/4
001: f(X
IN
)/8 or f(X
CIN
)/8
010: f(X
IN
)/16 or f(X
CIN
)/16
011: f(X
IN
)/32 or f(X
CIN
)/32
100: f(X
IN
)/64 or f(X
CIN
)/64
101: f(X
IN
)/128 or f(X
CIN
)/128
110: f(X
IN
)/256 or f(X
CIN
)/256
111: f(X
IN
)/512 or f(X
CIN
)/512
Auto-transfer interval set bit
00000: 2 cycles of transfer clock
00001: 3 cycles of transfer clock
:
11110: 32 cycles of transfer clock
11111: 33 cycles of transfer clock
Written to latch
Read from decrement counter
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