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参数资料
| 型号： | M38748EAF-XXXFS |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 44/92页 |
| 文件大小： | 1292K |
| 代理商： | M38748EAF-XXXFS |
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44
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(3) Arbitrary bit serial I/O mode
Since read and write of the serial I/O3 register are controlled by
the serial I/O3 automatic transfer controller, address 0013
16
func-
tions as the transfer counter (in byte units).
After the serial I/O3 automatic transfer data pointer and automatic
transfer interval set bits have been set, and an internal synchro-
nous clock selected, serial automatic transfer starts when the
value of the number of transfer bits decremented by 1 is written to
the transfer counter (address 0013
16
), just as in the automatic
transfer serial I/O. When selecting an external synchronous clock,
write the value of the transfer bits decremented by 1 to the trans-
fer counter, then input the transfer clock to S
CLK3
after 5 or more
cycles of internal clock
φ
. The transfer interval after each 8-bit data
transfer must be 5 or more cycles of internal clock
φ
after the ris-
ing edge of the last bit of the 8-bit data.
When selecting an internal synchronous clock, the automatic
transfer interval can be specified regardless of the contents of the
selected handshake signal.
In this case, when the automatic transfer interval setting is valid
and S
BUSY3
output is used there are the transfer interval before
the first data is transmitted/received, as well as after the last data
is transmitted/received just as in the automatic transfer serial I/O
mode. When using S
STB3
output, this transfer interval become 2
cycles longer than the value set for each 8-bit data. In addition,
when using the combined output of S
BUSY3
and S
STB3
, the trans-
fer interval after completion of transmission/receipt of the last data
become 2 cycles longer than the set value.
Fig. 38 Automatic transfer serial I/O operation
When selecting an external synchronous clock, the automatic
transfer interval cannot be specified.
Regardless of internal or external synchronous clock, the auto-
matic transfer data pointer is decremented after each 8-bit data is
received and then written to the auto-transfer RAM. The transfer
counter is decremented with the transfer clock. The serial transfer
status flag is set to “1” by writing to the transfer counter which trig-
gers the start of transmission. After the last data is written to the
automatic transfer RAM, the serial transfer status flag is set to “0”
and a serial I/O3 interrupt request occurs simultaneously.
The write values of the automatic transfer data pointer set bits and
the automatic transfer interval set bits are kept in the latch. As a
transfer counter write occurs, each value is transferred to its corre-
sponding decrement counter.
If the last data does not fill 8 bits, the receive data stored in the se-
rial I/O3 automatic transfer RAM become the closest MSB odd bit
if the transfer direction select bit is set to LSB first, or the closest
LSB odd bit if the transfer direction select bit is set to MSB first.
2FF
16
Automatic transfer RAM
Transfer counter
Automatic transfer
data pointer
Serial I/O3 register
252
16
251
16
250
16
24F
16
24E
16
200
16
04
16
52
16
S
IN3
S
OUT3
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| M38748EAF-XXXGP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M38748EDF-XXXFS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M38748EAF-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EAT-XXXFS | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EAT-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EBD-XXXFS | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38748EBD-XXXGP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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