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参数资料
| 型号： | M5M5Y5672TG-20 |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（262144 - Word的72位）网络的SRAM |
| 文件页数： | 21/27页 |
| 文件大小： | 240K |
| 代理商： | M5M5Y5672TG-20 |
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MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
21
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for
long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused
for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the
Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins.
EXTEST-A
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic
0s. The EXTEST command dose not block or override the SRAM's input pins; therefore, the SRAM's internal state is still determined by
its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register's contents, in parallel, on the SRAM's data output drivers on the falling edge of
TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the state of all SRAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are
transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the SRAM's output pins
drive out the value of the Boundary Scan Register location with which each output pin is associated.
The EXTEST implementation in this device dose not, without further user intervention, actually move the contents of the scan chain
onto the SRAM's output pins. Therefore this device is not strictly 1149.1-compliant. To push data from the Boundary Scan Registers, in
parallel, out onto the SRAM's I/O and output pins, the SRAM's main clock (CK) must be pulsed. A single CK transition is sufficient to
transfer the data, but more transitions will do no harm.
IDCODE
The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places
the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at
power-up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and
the Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state.
RFU
These instructions are reserved for future use. Do not use these instructions.
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