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参数资料
| 型号： | M5M5Y5672TG-20 |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（262144 - Word的72位）网络的SRAM |
| 文件页数： | 8/27页 |
| 文件大小： | 240K |
| 代理商： | M5M5Y5672TG-20 |
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MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
8
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
DC OPERATED TRUTH TABLE
Name
Input Status
HIGH or NC
LOW
Operation
Interleaved Burst Sequence
Linear Burst Sequence
LBO#
Note5. LBO# is DC operated pin.
Note6. NC means No Connection.
Note7. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
(2) Linear Burst Sequence (when LBO# = LOW)
Operation
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
Note8. The burst sequence wraps around to its initial state upon completion.
A17~A2
A17~A2
latched A17~A2
latched A17~A2
latched A17~A2
A1,A0
0 , 0
0 , 1
1 , 0
1 , 1
0 , 1
0 , 0
1 , 1
1 , 0
1 , 0
1 , 1
0 , 0
0 , 1
1 , 1
1 , 0
0 , 1
0 , 0
A17~A2
A17~A2
latched A17~A2
latched A17~A2
latched A17~A2
A1,A0
0 , 0
0 , 1
1 , 0
1 , 1
0 , 1
1 , 0
1 , 1
0 , 0
1 , 0
1 , 1
0 , 0
0 , 1
1 , 1
0 , 0
0 , 1
1 , 0
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| M5M80011A | 制造商:Mitsubishi Electric 功能描述: |
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