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参数资料
型号： M7020R-083ZA1T
厂商： 意法半导体
英文描述： 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述： 32K的× 68位进入网络搜索引擎
文件页数： 132/150页
文件大小： 996K
代理商： M7020R-083ZA1T
M7020R
132/150
SRAM READ with a Table of Up to 31 Devices
The following explains the SRAM READ operation
accomplished through a table of up to 31 devices,
using the following parameters: TLSZ = 10. The di-
agram of such a table is shown in Figure 97, page
133.
The following assumes that SRAM access is being
accomplished through M7020R Device 0 and that
Device 0 is the selected device. Figure 98, page
134 and Figure 99, page 135 show the timing dia-
grams for Device 0 and Device 30, respectively.
–
Cycle 1A:
The host ASIC applies the READ In-
struction to CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address, with DQ[20:19] set to
'10,' to select the SRAM address. The host
ASIC selects the device for which the ID[4:0]
matches the DQ[25:21] lines. During this cycle,
the host ASIC also supplies SADR[21:20] on
CMD[8:7].
–
Cycle 1B:
The host ASIC continues to apply the
READ Instruction to CMD[1:0] using CMDV = 1.
The DQ Bus supplies the address, with
DQ[20:19] set to '10,' to select the SRAM ad-
dress.
–
Cycle 2:
The host ASIC floats DQ[67:0] to a 3-
state condition.
–
Cycle 3:
The host ASIC keeps DQ[67:0] in a 3-
state condition.
–
Cycle 4:
The selected device starts to drive
DQ[67:0].
–
Cycles 5 to 6:
The selected device continues to
drive DQ[67:0].
–
Cycle 7:
The selected device continues to drive
DQ[67:0] and drives an SRAM READ cycle.
–
Cycle 8:
The selected device drives ACL from Z
to low.
–
Cycle 9:
The selected device drives ACK to
high.
–
Cycle 10:
The selected device drives ACK from
high to low.
At the end of Cycle 10, the selected device floats
ACL in a 3-state condition.
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