参数资料
型号: MAX16067ETJ+T
厂商: Maxim Integrated Products
文件页数: 28/48页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0’. If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1’. A
connected processor can check this bit to see the reset
was due to a watchdog timeout.
See Table 23 for more information on configuring watch-
dog functionality.
Independent Watchdog Timer Operation
When r73h[4] is ‘1,’ the watchdog timer operates in
the independent mode. In the independent mode, the
watchdog timer operates as if it were a separate device.
The watchdog timer is activated immediately upon V CC
V TH
LAST MON_
WDI
exceeding UVLO and once the boot-up sequence is fin-
ished. When RESET is asserted by the sequencer state
machine, the watchdog timer and WDO are not affected.
There is a startup delay if r76h[6:4] is set to a value dif-
ferent than ‘000’. If r76h[6:4] is set to ‘000’, there is not a
startup delay. See Table 23 for delay times.
In independent mode, if the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘1,’ when the watchdog
timer expires, WDO asserts then RESET asserts. WDO
is then deasserts. WDO is low for approximately 1 F s. If
the Watchdog Reset Output Enable bit (r76h[7]) is set to
‘0,’ when the watchdog timer expires, WDO asserts but
RESET is not affected.
< t WDI
t WDI_STARTUP
< t WDI
tRP
RESET
Figure 6. Normal Watchdog Startup Sequence
V CC
WDI
< t WDI
< t WDI
< t WDI
> t WDI
< t WDI
< tWDI
< t WDI
0V
t WDI
V CC
WDO
0V
Figure 7. Watchdog Timer Operation
28
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