参数资料
型号: MAX16067ETJ+T
厂商: Maxim Integrated Products
文件页数: 37/48页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
SMBALERT ( ALERT )
The MAX16067 supports the SMBus alert protocol. To
enable the SMBus alert output, set r40h[4] to ‘1’, then
configure GPIO1 to act as the SMBus alert ( ALERT )
according to Table 11. This output is open drain and
uses the wired-OR configuration with other devices
on the SMBus. During a fault, the MAX16067 asserts
ALERT low, signaling the master that an interrupt has
occurred. The master responds by sending the ARA
(Alert Response Address) protocol on the SMBus. This
protocol is a read byte with 09h as the slave address.
The slave acknowledges the ARA (09h) address and
sends its own SMBus address to the master. The slave
then deasserts ALERT . The master can then query the
slave and determine the cause of the fault. By checking
r1C[7], the master can confirm that the MAX16067 trig-
REGISTERS
AND EEPROM
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
MEMORY READ REGISTER
[LENGTH = 8 BITS]
gered the SMBus alert. The master must send the ARA
before clearing r1Ch[7]. Clear r1Ch[7] by writing a ‘1’. If
GPIO1 is configured as the SMBus alert output but the
SMBus alert feature is disabled (r40h[4] is set to ‘0’),
GPIO1 acts as an additional fault output.
JTAG Serial Interface
The MAX16067 features a JTAG port that complies with
a subset of the IEEE ? 1149.1 specification. Either the
SMBus or the JTAG interface can be used to access
internal memory; however, only one interface is allowed
to run at a time. The MAX16067 contains extra JTAG
instructions and registers not included in the JTAG
specification that provide access to internal memory.
The extra instructions include LOAD ADDRESS, WRITE
DATA, READ DATA, REBOOT, and SAVE.
01100
01011
01010
01001
01000
00111
00110
MUX 1
00101
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
00100
COMMAND
DECODER
USER CODE REGISTER
[LENGTH = 32 BITS]
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
00011
00000
11111
01100
01011
01010
01001
01000
00111
SETFLSHADD
RSTFLSHADD
RSTUSRFLSH
SETUSRFLSH
SAVE
REBOOT
V DB
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
R PU
TDI
MUX 2
TDO
TMS
TCK
TEST ACCESS PORT
(TAP) CONTROLLER
Figure 13. JTAG Block Diagram
IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.
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