参数资料
型号: MAX16067ETJ+T
厂商: Maxim Integrated Products
文件页数: 43/48页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
so that all faults propagate between devices. If a critical
fault occurs on one device, EXTFAULT asserts, triggering
the nonvolatile fault logger in all cascaded devices and
recording a snapshot of all system voltages.
U Connect open-drain RESET outputs together to obtain
a master system reset signal.
U Connect all EN inputs together for a master enable sig-
nal. Since the internal timings of each cascaded device
are not synchronized, EN_OUT_s placed in the same
slot on different devices do not come up in the desired
order even if the sequence delays are identical.
U Consider using an external F P to control the EN inputs
or the software enable bits of cascaded devices, mon-
itoring the RESET outputs as a power-good signal.
U For a large number of voltage rails, the MAX16067
can be cascaded hierarchically by using one master
device’s EN_OUT_s to control the EN inputs of several
slave devices.
Controlling Power Supplies
Without Using the Sequencer
A F P can control power supplies manually without involv-
ing the sequencing slot system by controlling EN_OUT_s
configured as GPIO. The output of a power supply con-
trolled this way can be monitored using a MON_ input
configured as “monitoring only” (see the Monitoring
Inputs While Sequencing section). To monitor the sup-
ply for critical faults, the F P will need to manually set the
critical fault enable bit in r6Eh–r72h after turning on the
EN_OUT_, and manually clearing the critical fault enable
bit before turning off the EN_OUT_.
Layout and Bypassing
Bypass DBP and ABP each with a 1 F F ceramic capacitor
to GND. Bypass V CC with a 10 F F capacitor to ground.
Avoid routing digital return currents through a sensitive
analog area, such as an analog supply input return path
or ABP’s bypass capacitor ground connection. Use
dedicated analog and digital ground planes. Connect
the capacitors as close as possible to the device.
Figure 17. Graphical User Interface Screenshot
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