参数资料
型号: MAX16067ETJ+T
厂商: Maxim Integrated Products
文件页数: 30/48页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
User-Defined Register
Register r8Ah provides storage space for a user-defined
configuration or firmware version number. Note that this
register controls the contents of the JTAG USERCODE
register bits 7-0. The user-defined register is stored at
r28Ah in the flash memory.
Memory Lock Bits
Register r8Ch contains the lock bits for the configuration
registers, configuration flash, user flash, and fault regis-
ter lock. See Table 24 for details.
SMBus-Compatible Serial Interface
The MAX16067 features an SMBus-compatible, 2-wire
serial interface consisting of a serial-data line (SDA)
and a serial-clock line (SCL). SDA and SCL facilitate
bidirectional communication between the MAX16067
and the master device at clock rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX16067 is a transmit/receive, slave-only device, rely-
ing upon a master device to generate a clock signal.
The master device (typically a microcontroller) initiates
a data transfer on the bus and generates SCL to permit
that transfer.
A master device communicates to the MAX16067 by
transmitting the proper address followed by command
and/or data words. The slave address input, A0, is
capable of detecting four different states, allowing mul-
tiple identical devices to share the same serial bus. The
slave address is described further in the Slave Address
section. Each transmit sequence is framed by a START
Table 24. Memory Lock Bits
(S) or REPEATED START (Sr) condition and a STOP (P)
condition. Each word transmitted over the bus is 8 bits
long and is always followed by an acknowledge pulse.
SCL is a logic input, while SDA is an open-drain input/
output. SCL and SDA both require external pullup resis-
tors to generate the logic-high voltage. Use 4.7k I for
most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 9);
otherwise, the MAX16067 registers a START or STOP
condition (Figure 10) from the master. SDA and SCL idle
high when the bus is not busy.
START and STOP Conditions
A master device signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. The master device issues a STOP
condition by transitioning SDA from low to high while
SCL is high. A STOP condition frees the bus for another
transmission. The bus remains active if a REPEATED
START condition is generated, such as in the block read
protocol (see Figure 1, SMBus Timing Diagram).
Early STOP Conditions
The MAX16067 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition. This condition
is not a legal SMBus format; at least one clock pulse must
separate any START and STOP condition.
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
Configuration Register Lock
[0]
[1]
1 = Locked
0 = Unlocked
Flash Fault Register Lock
1 = Locked
0 = Unlocked
8Ch
28Ch
[2]
[3]
[7.4]
Flash Configuration Lock
1 = Locked
0 = Unlocked
User Flash Lock
1 = Locked
0 = Unlocked
Not used
30
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