参数资料
型号: MAX17019ATM+T
厂商: Maxim Integrated Products
文件页数: 14/25页
文件大小: 0K
描述: IC VOLT CTRL QUAD OUT 48-TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 嵌入式系统,控制台/机顶盒
电源电压: 5.5 V ~ 38 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
High-Input-Voltage Quad-Output Controller
Pin Description (continued)
PIN
36
37
38
39
40–43
44
45
46
47
48
EP
NAME
FBB
ONB
SYNC
ONA
INBC
V DD
POKD
OND
ONC
FBC
PGND
FUNCTION
Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V.
Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven
high, the controller enables the 3A internal switching regulator.
External Synchronization Input. Used to override the internal switching frequency.
Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is
driven high, the controller enables the step-up/step-down converter.
Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of
the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10 μF or greater
ceramic capacitors to support the RMS current.
5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1μF or greater ceramic
capacitor. Provides power for the BSTB and BSTC driver supplies.
Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more
than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in
shutdown. POKD becomes high impedance when FBD is in regulation.
Source/Sink Linear Regulator (Regulator D) and Reference Buffer Enable Input. When OND is pulled low, OUTD
is high impedance. When OND is driven high, the controller enables the source/sink linear regulator.
Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven
high, the controller enables the 5A internal switching regulator.
Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V.
Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching
regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad.
Connect the exposed backside pad to system power ground planes through multiple vias.
Detailed Description
The MAX17019 standard application circuit (Figure 1)
provides a 5V/5A P-P main stage, a 1.8V/3A P-P VDDQ
and 0.9A/2A VTT outputs for DDR, and a 1.05V/5A P-P
chipset supply.
The MAX17019 supports four power outputs—one high-
voltage step-down controller, two internal MOSFET
step-down switching regulators, and one high-current
source/sink linear regulator. The step-down switching
regulators use a current-mode fixed-frequency architec-
ture compensated by the output capacitance. An inter-
nal 50mA 5V linear regulator provides the bias supply
and driver supplies, allowing the controller to power up
from input supplies greater than 5.5V.
Fixed 5V Linear Regulator (LDO5)
An internal linear regulator produces a preset 5V low-
current output from INLDO. LDO5 powers the gate dri-
vers for the external MOSFETs, and provides the bias
supply required for the SMPS analog controller, refer-
ence, and logic blocks. LDO5 supplies at least 50mA
for external and internal loads, including the MOSFET
gate drive, which typically varies from 5mA to 15mA
per switching regulator, depending on the switching
frequency. Bypass LDO5 with a 4.7 μF or greater
ceramic capacitor to guarantee stability under the full-
load conditions.
The MAX17019 switch-mode step-down switching reg-
ulators require a 5V bias supply in addition to the main-
power input supply. This 5V bias supply is generated
by the controller’s internal 5V linear regulator (LDO5).
This boot-strappable LDO allows the controller to
power up independently. The gate driver V DD input
supply is typically connected to the fixed 5V linear reg-
ulator output (LDO5). Therefore, the 5V LDO supply
must provide LDO5 (PWM controller) and the gate-
drive power during power-up.
14
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