参数资料
型号: MAX17019ATM+T
厂商: Maxim Integrated Products
文件页数: 24/25页
文件大小: 0K
描述: IC VOLT CTRL QUAD OUT 48-TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 嵌入式系统,控制台/机顶盒
电源电压: 5.5 V ~ 38 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
High-Input-Voltage Quad-Output Controller
VTT LDO Output Capacitor
Selection (C OUTD )
A minimum value of 20μF or greater ceramic is needed
to stabilize the VTT output (OUTD). This value of capac-
itance limits the switching regulator’s unity-gain band-
width frequency to approximately 1.2MHz (typ) to allow
adequate phase margin for stability. To keep the
capacitor acting as a capacitor within the switching
regulator ’s bandwidth, it is important that ceramic
capacitors with low ESR and ESL be used.
Since the gain bandwidth is also determined by the
transconductance of the output MOSFETs, which
increases with load current, the output capacitor might
need to be greater than 20 μF if the load current
exceeds 1.5A, but can be smaller than 20μF if the maxi-
mum load current is less than 1.5A. As a guideline,
choose the minimum capacitance and maximum ESR
for the output capacitor using the following:
VTT LDO Power Dissipation
Power loss in the MAX17019 VTT LDO is significant and
can become a limiting design factor in the overall
MAX17019 design:
PD VTT = 2A x 0.9V = 1.8W
The 1.8W total power dissipation is within the 40-pin
TQFN multilayer board power-dissipation specification
of 2.9W. The typical DDR termination application does
not actually continuously source or sink high currents.
The actual VTT current typically remains around 100mA
to 200mA under steady-state conditions. VTTR is down
in the microampere range, though the Intel specifica-
tion requires 3mA for DDR1 and 1mA for DDR2. True
worst-case power dissipation occurs on an output
short-circuit condition with worst-case current limit. The
MAX17019 does not employ any foldback current limit-
ing, and relies on the internal thermal shutdown for pro-
tection. Both the VTT and VTTR output voltages are
referenced to the same REFIND input.
and:
C OUT _ MIN = 20 μF ×
R ESR _ MAX = 5 m Ω ×
I LOAD
1 . 5 A
I LOAD
1 . 5 A
Applications Information
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). For the best
dropout performance, use the slowest switching fre-
quency setting (FREQ = GND). However, keep in mind
R ESR value is measured at the unity-gain-bandwidth
frequency given by approximately:
that the transient performance gets worse as the step-
down regulators approach the dropout voltage, so bulk
output capacitance must be added (see the voltage sag
f GBW =
36
C OUT
×
I LOAD
1 . 5 A
and soar equations in the SMPS Design Procedure
(Step-Down Regulators) section). The absolute point of
dropout occurs when the inductor current ramps down
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
during the off-time ( Δ I DOWN ) as much as it ramps up
during the on-time ( Δ I UP ). This results in a minimum
operating voltage defined by the following equation:
V IN ( MIN ) = V OUT CHG + h ?
+ V
- 1 ? ( V OUT DIS )
+ V
capacitor (if desired) to further suppress noise or volt-
age ripple at the output.
VTTR Output Capacitor Selection
? 1
? D MAX
?
?
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Therefore, the VTTR compensation requirements also
scale. For typical applications requiring load currents
up to ±3mA, a 0.22μF or greater ceramic capacitor is
recommended (R ESR < 0.3 Ω ).
where V CHG and V DIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
24
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