参数资料
型号: MAX17019ATM+T
厂商: Maxim Integrated Products
文件页数: 17/25页
文件大小: 0K
描述: IC VOLT CTRL QUAD OUT 48-TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 嵌入式系统,控制台/机顶盒
电源电压: 5.5 V ~ 38 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
High-Input-Voltage Quad-Output Controller
LDO5 Bootstrap Switchover
When the bypass input (BYP) exceeds the LDO5 boot-
strap-switchover threshold for more than 500μs, an
internal 1.5 Ω (typ) p-channel MOSFET shorts BYP to
LDO5, while simultaneously disabling the LDO5 linear
regulator. This bootstraps the controller, allowing power
for the internal circuitry and external LDO5 loading to
be generated by the output of a 5V switching regulator.
Bootstrapping reduces power dissipation due to driver
and quiescent losses by providing power from a
switch-mode source, rather than from a much-less-effi-
cient linear regulator. The current capability increases
from 50mA to 100mA when the LDO5 output is
switched over to BYP. When BYP drops below the boot-
strap threshold, the controller immediately disables the
bootstrap switch and reenables the 5V LDO.
Reference (REF)
The 1.25V reference is accurate to ±1% over temperature
and load, making REF useful as a precision system refer-
ence. Bypass REF to GND with a 0.1μF or greater ceram-
ic capacitor. The reference sources up to 50μA and sinks
5μA to support external loads. If highly accurate specifi-
cations are required for the main SMPS output voltages,
the reference should not be loaded. Loading the refer-
ence slightly reduces the output voltage accuracy
because of the reference load-regulation error.
V L
SMPS Detailed Description
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums multiple
signals: the output voltage-error signal with respect to
the reference voltage, the current-sense signal, and the
slope compensation ramp (Figure 3). The MAX17019
uses a direct-summing configuration, approaching
ideal cycle-to-cycle control over the output voltage
without a traditional error amplifier and the phase shift
associated with it.
Frequency Selection (FREQ)
The FREQ input selects the PWM mode switching fre-
quency. Table 1 shows the switching frequency based
on the FREQ connection. High-frequency (FREQ =
GND) operation optimizes the application for the small-
est component size, trading off efficiency due to higher
switching losses. This might be acceptable in ultra-
portable devices where the load currents are lower.
Low-frequency (FREQ = 5V) operation offers the best
overall efficiency at the expense of component size and
board space.
R1
R2
UNCOMPENSATED
TO PWM
LOGIC
FB_
HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
I1
I2
I3
V BIAS
REF
CSH_
CSL_
SLOPE COMPENSATION
Figure 3. PWM Comparator Functional Diagram
______________________________________________________________________________________
17
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