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参数资料
| 型号： | MAX17100ETM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/35页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST INT-SWITCH 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | LCD 电视机/监控器 |
| 电源电压： | 2.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Internal-Switch Boost Regulator with Integrated Scan
Driver, VCOM Calibrator, and Op Amp for TFT LCDs
Pin Description
PIN
1
2
3
4
5, 42
6
7
8
9
10, 11
12
13
14
15
16
17
18
19, 26
20
21
22
23
24
25
NAME
COMP
DRVN
FBN
REF
AGND
FBP
DRVP
TGS
GHON
GHD_
GOFF
CKBH2
CKH2
STH2
CKBH1
CKH1
STH1
YV1C_
CKB2
CK2
CKB1
CK1
ST2
ST1
FUNCTION
Step-Up Regulator Error-Amplifier Compensation Pin. Connect a series RC from COMP to AGND.
Gate-Off Linear-Regulator Base-Drive Output. Open drain of an internal n-channel MOSFET. Connect DRVN
to the base of an external npn pass transistor.
Gate-Off Linear Regulator Feedback Input. FBN regulates to 250mV (nominal). Connect FBN to the center of
a resistive voltage-divider between the negative output and REF to set the gate-off linear-regulator output
voltage. Place the resistive voltage-divider within 5mm of FBN.
Reference Output. Bypass REF to AGND with a minimum 0.22μF capacitor close to the pin. All power
outputs are disabled until REF exceeds its UVLO threshold.
Analog Ground. Connect to power ground (PGND) under the IC.
Gate-On Linear-Regulator Feedback Input. FBP regulates to 1.25V (nominal). Connect FBP to the center of a
resistive voltage-divider between the positive charge-pump regulator output and AGND to set the gate-on
linear-regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
Gate-On Linear-Regulator Base-Drive Output. Open drain of an internal n-channel MOSFET. Connect DRVP
to the base of an external pnp pass transistor.
High-Voltage-Switch Delay Input. Connect a capacitor from TGS to AGND to set the high-voltage-switch
startup delay.
High-Voltage-Switch Input. Source of the internal high-voltage p-channel MOSFET. Bypass GHON to PGND
with a minimum of 0.1μF capacitor close to the pin.
High-Voltage-Switch Input. Drain of the internal high-voltage back-to-back p-channel MOSFETs.
Gate-Off Voltage Input for Level Shifter
Level-Shifter Output
Level-Shifter Output
Level-Shifter Output
Level-Shifter Output
Level-Shifter Output
Level-Shifter Output
High-Voltage-Switch Control Input. When YV1C_ is high, the high-voltage switch between GHON and GHC_
is on and the high-voltage switch between GHC_ and GHD_ is off. When YV1C_ is low, the switch between
GHON and GHC_ is off and the switch between GHC_ and GHD_ is on. YV1C_ is inhibited by the IN
undervoltage lockout and when the voltage on TGS is less than 1.25V.
Level-Shifter Logic-Level Input
Level-Shifter Logic-Level Input
Level-Shifter Logic-Level Input
Level-Shifter Logic-Level Input
Level-Shifter Logic-Level Input
Level-Shifter Logic-Level Input
14
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