参数资料
型号: MAX17100ETM+T
厂商: Maxim Integrated Products
文件页数: 28/35页
文件大小: 0K
描述: IC REG BOOST INT-SWITCH 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: LCD 电视机/监控器
电源电压: 2.5 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
Internal-Switch Boost Regulator with Integrated Scan
Driver, VCOM Calibrator, and Op Amp for TFT LCDs
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (h FE(MIN) ), input capacitance, collector-emitter
saturation voltage, and power dissipation. The transis-
tor’s current gain limits the guaranteed maximum output
current to:
where V T is 26mV at room temperature and I BIAS is the
current through the base-to-emitter resistor (R BE ). For
the MAX17100, the bias currents for both the gate-on
and gate-off linear-regulator controllers are 0.1mA.
Therefore, the base-to-emitter resistor for both linear
regulators should be chosen to set 0.1mA bias current:
I LOAD(MAX) DRV - BE ) × h FE(MIN)
V BE 0.7V
=(I
V
R BE
R BE =
=
0.1mA 0.1mA
= 6.8k ?
where I DRV is the minimum guaranteed base-drive cur-
rent, V BE is the transistor’s base-to-emitter forward volt-
age drop, and R BE is the pullup resistor connected
between the transistor’s base and emitter. Furthermore,
the transistor’s current gain increases the linear regula-
tor’s DC loop gain (see the Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
maximum output current can be difficult to stabilize and
are not recommended unless the high gain is needed
to meet the load-current requirements.
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capaci-
tor’s ESR generates a zero. For proper operation, use
the following equations to verify the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator can support.
f POLE_LR =
I LOAD(MAX)_LR
2 × C OUT_LR × V OUT_LR
Also, the package’s power dissipation limits the usable
maximum input-to-output voltage differential. The maxi-
mum power-dissipation capability of the transistor’s
package and mounting must exceed the actual power
dissipated in the device. The power dissipated equals
the maximum load current (I LOAD(MAX)_LR ) multiplied
by the maximum input-to-output voltage differential:
P = I LOAD(MAX)_LR × (V IN(MAX)_LR - V OUT_LR )
The unity-gain crossover of the linear regulator is:
f CROSSOVER = A V_LR x f POLE_LR
2) The pole created by the internal amplifier delay is
approximately 1MHz:
f POLE_AMP = 1MHz
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and
the base-to-emitter pullup resistor:
where V IN(MAX)_LR is the maximum input voltage of the
linear regulator and V OUT_LR is the output voltage of
the linear regulator.
f POLE_IN =
1
2 × C I N × (R BE //R IN )
C IN = m , R IN = FE
Stability Requirements
The MAX17100 linear-regulator controllers use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, the
pass transistor, the base-emitter resistor, and the out-
put capacitor determine the loop stability. The following
applies to both linear-regulator controllers in the
MAX17100.
where:
g h
2 f T g m
g m is the transconductance of the pass transistor and f T
is the transition frequency. Both parameters can be found
in the transistor’s data sheet. Because R BE is much
greater than R IN , the above equation can be simplified:
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
f POLE_IN =
1
2 π × C IN × R IN
) × [1 + ( BIAS
A V_LR ? (
10
V T
I × h EF
I LOAD_LR
)] × V REF
28
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