参数资料
型号: MAX17100ETM+T
厂商: Maxim Integrated Products
文件页数: 29/35页
文件大小: 0K
描述: IC REG BOOST INT-SWITCH 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: LCD 电视机/监控器
电源电压: 2.5 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 带卷 (TR)
Internal-Switch Boost Regulator with Integrated Scan
Driver, VCOM Calibrator, and Op Amp for TFT LCDs
f POLE_IN = T
Substituting for C IN and R IN yields:
f
h FE
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and AGND (including stray capacitance):
the output diode. If the step-up regulator has 90% effi-
ciency, approximately 3% to 5% of the power is lost in
the internal MOSFET, approximately 3% to 4% in the
inductor, and approximately 1% in the output diode. The
remaining 1% to 3% is distributed among the input and
output capacitors and the PCB traces. If the input power
is about 5W, the power lost in the internal MOSFET is
approximately 150mW to 250mW. Use the following for-
f POLE_FB =
1
2 π × C FB × (R UPPER //R LOWER )
mula to estimate the power loss on the built-in power
MOSFET:
P LX_ON ≈ (I IN(DC,MAX) × D ) 2 × R DSON
where C FB is the capacitance between FB_ and AGND,
R UPPER is the upper resistor of the linear regulator’s
feedback divider, and R LOWER is the lower resistor of
the divider.
5) Next, calculate the zero caused by the output
capacitor’s ESR:
where R DSON is the on-resistance for the power
MOSFET. The switching losses have not been account-
ed for in this calculation.
Level-Shifting Scan Driver
The power dissipation in the IC per level-shifter output
f POLE_ESR =
1
2 π × C OUT_LR × R ESR
depends on the level-shifter operating frequency (f LS ),
the voltage differential between V GHON and V GOFF ,
and the level-shifter output resistance.
The power for each dissipation each channel can be
C (V - V ) 2 × f LS
P LSO = PANEL GHON GOFF
where  R ESR is  the  equivalent  series  resistance  of
C OUT_LR . To ensure stability, choose C OUT_LR large
enough so the crossover occurs well before the poles
and zero calculated in steps 2 to 5. The poles in steps
calculated by:
2
R d1 R d2
3  and  4  generally  occur  at  several  megahertz,  and
using ceramic capacitors ensures the ESR zero occurs
at several megahertz as well. Placing the crossover
× (
+
R PANEL + R d1 R PANEL +R d2
)
below 500kHz is sufficient to avoid the amplifier-delay
pole and generally works well, unless unusual compo-
nent choices or extra capacitances move one of the
other poles or the zero below 1MHz.
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PCB copper area,
other thermal mass, and airflow. More PCB copper,
cooler ambient air, and more airflow increase the possi-
ble dissipation, while less copper or warmer air
decreases the IC’s dissipation capability. The major
components of power dissipation are the power dissi-
pated in the step-up regulator and the power dissipat-
ed by the operational amplifiers.
Step-Up Regulator
The largest portions of power dissipation in the step-up
regulator are the internal MOSFET, the inductor, and
where R PANEL and C PANEL are the equivalent resis-
tance and capacitance of the panel, R d1 and R d2 are
the output resistance of the scan drivers.
Since two channels (STH1, STH2) are used as the start-
pulse signal, the operating frequency is much lower
compared to other channels. The power dissipation for
both channels can be ignored.
Operational Amplifiers
The power dissipated in the operational amplifier (includ-
ing programmable VCOM calibrator) depends on the out-
put current, the output voltage, and the supply voltage:
PD SOURCE =I OUT_SOURCE × ( V SUP - V OUT )
PD SINK = I OUT_SINK × V OUT
where I OUT_SOURCE is the output current sourced by
the operational amplifier and I OUT_SINK is the output
current that the operational amplifier sinks.
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