参数资料
型号: MAX17409GTI+T
厂商: Maxim Integrated Products
文件页数: 11/32页
文件大小: 0K
描述: IC CTRLR NVIDIA CPU 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 处理器
电流 - 电源: 1.5mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
1-Phase Quick-PWM GPU Controller
Pin Description (continued)
PIN
7
8
9
10
11 –16
17
18
19
20
21
NAME
THRM
TON
PWRGD
SHDN
G0 –G5
PGND
DL
V DD
BST
LX
FUNCTION
Comparator Input for Thermal Protection. THRM connects to the positive input of an internal
comparator. The comparator’s negative input connects to an internal resistive voltage-divider that
accurately sets the THRM threshold to 30% of the V CC voltage. Connect the output of a resistor-
divider and thermistor-divider (between V CC and GND) to THRM with the values selected so the
voltage at THRM falls below 30% of V CC (1.5V when V CC = 5V) at the desired high temperature.
Switching Frequency-Setting Input. An external resistor (R TON ) between the input power source and
TON sets the switching frequency (f SW = 1/t SW ) according to the following equation used to
determine the nominal switching period:
t SW = 16.3pF x (R TON + 6.5k )
TON enters a high impedance in shutdown to reduce the input quiescent current. If the TON current
is less than 10μA, the MAX17409 disables the controller, sets the TON OPEN fault latch, and pulls
DH and DL low.
Open-Drain Power-Good Output. The MAX17409 forces PWRGD low when SHDN is pulled low. After
the controller is properly powered up, PWRGD becomes a high-impedance output as long as the
feedback voltage is in regulation and the startup blanking time has expired.
PWRGD becomes active 5ms after the MAX17409 reaches the VID target. The MAX17409 pulls
PWRGD low when shutdown ( SHDN = GND) is pulled low, during startup, and during shutdown
transitions.
The PWRGD upper threshold is blanked during any downward output-voltage transition that occurs
when the MAX17409 is in skip mode (SKIP = V CC ). PWRGD remains blanked until the transition-
related PWRGD blanking period expires and the controller detects the output is in regulation (error-
amplifier edge occurs).
Note: The pullup resistance on PWRGD causes additional shutdown current.
Shutdown Control Input. Connect to V CC for normal operation. Connect to ground to put the
controller into the low-power 1μA (max) shutdown state. During startup, the controller ramps up the
output voltage with a 1.56mV/μs slew rate to the selected target voltage. During the shutdown
transition, the MAX17409 softly ramps down the output voltage with a 1.56mV/μs slew rate. Forcing
SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and thermal
shutdown, and clears the fault latches.
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The G0 –G5 inputs do not have internal pullups.
These 1.0V logic inputs are designed to interface directly with the μP. The output voltage is set by
the DAC code indicated by the logic-level voltages on G0 –G5.
Power Ground. Ground connection for the DL driver.
Low-Side Gate-Driver Output. DL swings from V DD to PGND. DL is forced low in shutdown. DL is
also forced low when an output overvoltage fault is detected, overriding any negative current-limit
condition that might be present. DL is forced low in skip mode after detecting an inductor current
zero crossing.
Driver-Supply Voltage Input. V DD supplies power to the low-side gate driver (DL) and to the internal
BST switch used to refresh the BST capacitor. Connect V DD to the 4.5V to 5.5V system supply
voltage. Bypass V DD to PGND with a 1μF or greater ceramic capacitor.
Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate
driver. An internal switch between V DD and BST charges the flying capacitor while the low-side
MOSFET is on (DL pulled high and LX pulled to ground).
Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. The
MAX17409 also uses LX as the input to the zero-crossing comparator.
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11
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