参数资料
型号: MAX17409GTI+T
厂商: Maxim Integrated Products
文件页数: 21/32页
文件大小: 0K
描述: IC CTRLR NVIDIA CPU 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 处理器
电流 - 电源: 1.5mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
1-Phase Quick-PWM GPU Controller
Output-Voltage Transition Timing
The MAX17409 performs mode transitions in a controlled
manner, automatically minimizing input surge currents.
This feature allows the circuit designer to achieve nearly
The slew rate is not dependent on the total output
capacitance, as long as the surge current is less than
the current limit. For all dynamic VID transitions, the
transition time (t TRAN ) is given by:
V NEW OLD
ideal transitions, guaranteeing just-in-time arrival at the
new output voltage level with the lowest possible peak
currents for a given output capacitance.
t TRAN =
- V
12 . 5 mVμs
At the beginning of an output-voltage transition, the
MAX17409 blanks both PWRGD thresholds, preventing
the PWRGD open-drain output from changing states
during the transition. The controller enables the
PWRGD thresholds approximately 20μs after the slew-
rate controller reaches the target output voltage. The
slew rate is set to 12.5mV/μs to ensure that the transi-
tion can be completed within a reasonable time period.
The MAX17409 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current source to transition the target
voltage. The total transition time depends on the
12.5mV/μs slew rate, the voltage difference, and the
accuracy of the slew-rate controller, C SLEW , accuracy).
where V OLD is the original output voltage, and V NEW is
the new target voltage. See Slew-Rate Accuracy in the
Electrical Characteristics for slew-rate limits. For soft-
start and shutdown, the controller automatically
reduces the slew rate to 1.56mV/μs (1/8 of the nominal
slew rate).
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current required to make an output voltage
transition is:
I L ? C OUT × 12 . 5 mVμs
where C OUT is the total output capacitance.
OVP LEVEL
OVP = 1.45V MIN
OVP TRACKS INTERNAL TARGET
HIGH VID
CPU CORE
VOLTAGE
VID (G0–G5)
INTERNAL
TARGET
ACTUAL V OUT
SLEEP VID
NEW ACTIVE
VID
LOW VID
SKIP
INTERNAL
PWM CONTROL
DH
PULSE-SKIPPING MODE
NO PULSES: V OUT > V TARGET
FORCED-PWM MODE
PWRGD
BLANK HIGH-Z
t BLANK
20 μ s TYP
LOW THRESHOLD ONLY
BLANK HIGH-Z
t BLANK
20 μ s TYP
Figure 4. VID Transition
______________________________________________________________________________________
21
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