参数资料
型号: MAX17409GTI+T
厂商: Maxim Integrated Products
文件页数: 23/32页
文件大小: 0K
描述: IC CTRLR NVIDIA CPU 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 处理器
电流 - 电源: 1.5mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
1-Phase Quick-PWM GPU Controller
Power-Up Sequence (POR, UVLO)
The MAX17409 is enabled when SHDN is driven high
(Figure 6). The reference powers up first. Once the ref-
erence exceeds its UVLO threshold, the internal analog
blocks are turned on and masked by a 150μs one-shot
delay. The PWM controller then begins switching.
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V CC UVLO circuitry
inhibits switching until V CC rises above 4.25V. The con-
troller powers up the reference once the system
enables the controller, V CC is above 4.25V, and SHDN
is driven high. With the reference in regulation, the con-
troller ramps the output voltage to the selected VID volt-
age with a 1.56mV/μs slew rate:
where V BOOT is the initial VID target. The soft-start cir-
cuitry does not use a variable current limit, so full output
current is available immediately. PWRGD becomes
high impedance approximately 5ms after the target out-
put voltage is reached. The MAX17409 automatically
uses pulse-skipping mode during soft-start and uses
forced-PWM mode during soft-shutdown, regardless of
the SKIP configuration.
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the V CC power supply below 0.5V.
If the V CC voltage drops below 4.25V, the controller
t TRAN ( START ) =
V BOOT
( 1 . 56 mV / μs )
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately
and forces a high-impedance output (DL and DH
pulled low).
V CC
SHDN
G0–G5 INVALID VID
INVALID VID CODE
OVP LEVEL
OVP = 1.45V MIN
OVP TRACKS INTERNAL TARGET
OVP = 1.45V MIN
SOFT-START =
1.56mV/ μ s SLEW RATE
SOFT-SHUTDOWN =
INITIAL TARGET
V CORE
1.56mV/ μ s SLEW RATE
INTERNAL
PWM CONTROL
PULSE SKIPPING
FORCED-PWM
PWRGD
t BLANK
60 μ s TYP
t BLANK
5ms TYP
t BLANK
20 μ s TYP
Figure 6. Power-Up and Shutdown Sequence Timing Diagram
t BLANK
20 μ s TYP
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