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| 型号： | MAX1897ETP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-TQFN |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
prevent the on times from overlapping. Therefore, the
instantaneous input current peaks of each phase do
not overlap, resulting in reduced input and output volt-
age ripple and RMS ripple current. This lowers the
input and output capacitor requirements, which allows
fewer or less expensive capacitors, and decreases
shielding requirements for EMI. When the on-times
overlap at low input-to-output differential voltages (V IN
< η V OUT ), the input currents of the overlapping phases
may sum together, increasing the total input and output
ripple voltage and RMS ripple current.
During in-phase operation, the input capacitors must
support large, instantaneous input currents when the
high-side MOSFETs turn on simultaneously, resulting in
increased ripple voltage and current when compared
to out-of-phase operation. The higher RMS ripple cur-
rent degrades efficiency due to power loss associated
with the input capacitor ’ s effective series resistance
(ESR). This typically requires a large number of low-
ESR input capacitors in parallel to meet input ripple
current ratings or minimize ESR-related losses.
For the MAX1897, the polarity select input (POL) deter-
mines whether rising edges (POL = V CC ) or falling
edges (POL = GND) trigger a new cycle. For low duty-
cycle applications (duty factor < 50%), triggering on
the rising edge of the master ’ s low-side gate driver pre-
vents both high-side MOSFETs from turning on at the
same time. Staggering the phases in this way lowers
the input ripple current, thereby reducing the input
capacitor requirements. For applications operating with
approximately a 50% duty factor, out-of-phase opera-
tion (POL = V CC ) causes the slave controller to com-
plete an on-pulse coincident to the master controller
determining when to initiate its next on-time. The noise
generated when the slave controller turns off its high-
side MOSFET could compromise the master controller ’ s
feedback voltage and current-sense inputs, causing
inaccurate decisions that lead to more jitter in the
switching waveforms. Under these conditions, trigger-
ing off of the falling edge (POL = GND) of the master ’ s
low-side gate driver forces the controllers to operate in-
phase, improving the system ’ s noise immunity.
put voltage. Another benefit of forced-PWM operation,
the switching frequency remains relatively constant
over the full load and input voltage ranges.
5V Bias Supply (V CC and V DD )
The MAX1887/MAX1897 require an external 5V bias
supply in addition to the battery. Typically this 5V bias
supply is the notebook ’ s 95% efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency, eliminates power dissipation limita-
tions, and removes the cost associated with the inter-
nal, 5V linear regulator that would otherwise be needed
to supply the PWM circuit and gate drivers. If stand-
alone capability is needed, the 5V supply can be gen-
erated with an external linear regulator.
The 20-pin MAX1897 has a separate analog PWM sup-
ply voltage input (V CC ) and gate-driver supply input
(V DD ). For the 16-pin MAX1887 device, the analog
PWM supply voltage input and the gate-driver supply
voltage input are internally connected and named V DD .
The battery input (V+) and 5V bias inputs (V CC and
V DD ) can be tied together if the input source is a fixed
4.5V to 5.5V supply.
The maximum current required from the 5V bias supply
to power V CC (PWM controller) and V DD (gate-drive
power) is:
I BIAS = I CC + f SW (Q G1 + Q G2 ) = 10mA to 45mA (typ)
where I CC is 525μA typical, f SW is the switching
frequency, and Q G1 and Q G2 are the MOSFET data
sheets ’ total gate charge specification limits at
V GS = 5V.
Shutdown (MAX1897 only)
When SHDN is driven low, the MAX1897 enters the
micropower shutdown mode (Table 3). Shutdown
immediately forces DL high, pulls DH low, and shuts
down the PWM controller so the total supply current
(I CC + I DD + I+) drops below 1μA. When SHDN is dri-
ven high, the MAX1897 operates normally with the
PWM controller enabled.
Table 3. Approximate K-Factor Errors
Forced-PWM Mode
The MAX1887/MAX1897 controllers do not allow light-
load pulse skipping. Therefore, the master controller
must be configured for forced-PWM operation. This
PWM control scheme forces the low-side gate drive
waveform to be the complement of the high-side gate
drive waveform, allowing the inductor current to
reverse. During negative load and downward output
voltage transitions, forced-PWM operation allows the
TON
CONNECTION
(MAX1897)*
V CC
Float
GND
FREQUENCY
SETTING
(kHz)
200
300
550
K-FACTOR
(μs)
5
3.3
1.8
MAX
K-FACTOR
ERROR
(%)
10
10
10
converter to sink current, rapidly pulling down the out-
* The MAX1887 is internally preset for 300kHz operation.
______________________________________________________________________________________
15
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