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| 型号： | MAX1897ETP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-TQFN |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
I LOAD ( SLAVE ) = I LOAD ( MASTER ) = LOAD
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moder-
ately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
V IN - V OUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low resistance, low inductance path from the DL
driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1887/MAX1897 will interpret the
MOSFET gate as “ off ” while there is actually charge still
left on the gate. Use very short, wide traces (50mils to
100mils wide if the MOSFET is 1 inch from the device).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4 ? (typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the LX node, due to capacitive coupling from the drain
to the gate of the low-side synchronous-rectifier MOS-
FET. However, for high-current applications, some com-
binations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor efficien-
cy, EMI, and shoot-through currents. This is often reme-
died by adding a resistor less than 5 ? in series with
BST, which increases the turn-on time of the high-side
FET without degrading the turn-off time (Figure 4).
Undervoltage Lockout
During startup, the V CC undervoltage lockout (UVLO)
circuitry forces the DL gate driver high and the DH gate
driver low, inhibiting switching until an adequate supply
voltage is reached. Once V CC rises above 3.75V, valid
transitions detected at the trigger input initiate a corre-
sponding on-time pulse (see the On-Time Control and
Active Current Balancing section). To ensure correct
startup, the MAX1887/MAX1897 slave controller ’ s
undervoltage lockout voltage must be lower than the
master controller ’ s undervoltage lockout voltage.
If the V CC voltage drops below 3.75V, it is assumed that
there is not enough supply voltage to make valid deci-
sions. To protect the output from overvoltage faults, DL
is forced high in this mode to force the output to
ground. This results in large negative inductor current
and possibly small negative output voltages. If V CC is
likely to drop in this fashion, the output can be clamped
with a Schottky diode to PGND to reduce the negative
excursion.
Thermal-Fault Protection
The MAX1887/MAX1897 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160 ° C, a thermal sensor activates the standby logic,
forces the DL low-side gate driver high, and pulls the
DH high-side gate driver low. This quickly discharges
the output capacitors, tripping the master controller ’ s
undervoltage lockout protection. The thermal sensor
reactivates the slave controller after the junction tem-
perature cools by 15 ° C.
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Input Voltage Range: The maximum value (V IN(MAX) )
must accommodate the worst-case high AC adapter
voltage. The minimum value (V IN(MIN) ) must account for
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Maximum Load Current: There are two values to con-
sider. The peak load current (I LOAD(MAX) ) determines
the instantaneous component stresses and filtering
requirements, and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current (I LOAD )
determines the thermal stresses and thus drives the
selection of input capacitors, MOSFETs, and other criti-
cal heat-contributing components. Modern notebook
CPUs generally exhibit I LOAD = I LOAD(MAX) ? 80%.
For multiphase systems, each phase supports a frac-
tion of the load, depending on the current balancing.
The highly accurate current sensing and balancing
implemented by the MAX1887/MAX1897 slave con-
troller evenly distributes the load among each phase:
I
η
where η is the number of phases.
Switching Frequency: This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are pro-
portional to frequency and V IN 2 . The optimum frequen-
cy also is a moving target, due to rapid improvements
18
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