参数资料
型号: MAX1897ETP+T
厂商: Maxim Integrated Products
文件页数: 26/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-TQFN
标准包装: 2,500
系列: Quick-PWM™
PWM 型: 控制器
输出数: 1
频率 - 最大: 550kHz
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 20-WQFN 裸露焊盘
包装: 带卷 (TR)
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
1.4V
VOLTAGE POSITIONING THE OUTPUT
A
V OUT
ESR VOLTAGE STEP
(I STEP x R ESR )
CAPACITIVE SOAR
(dV/dt = I OUT /C OUT )
1.4V
A. CONVENTIONAL CONVERTER (50mV/div)
B
CAPACITIVE SAG
(dV/dt = I OUT /C OUT )
RECOVERY
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
Figure 7. Voltage Positioning the Output
50mV x 21.3A = 1.06W,
which results in an overall power savings of:
35.2W - (33.03W + 1.06W) = 1.10W.
In effect, 2.2W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of dissipation away
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a nonvoltage-posi-
tioned circuit to equal the total dissipation of a voltage-
positioned circuit for a given CPU operating condition.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned cir-
cuit (V IN , I IN , V OUT , I OUT ).
2) Model the load resistance for each data point:
R LOAD = V OUT / I OUT
3) Calculate the output current that would exist for each
R LOAD data point in a nonpositioned application:
I NP = V NP / R LOAD
where V NP = 1.6V (in this example).
4) Calculate effective efficiency as:
Effective efficiency = (V NP ? I NP ) / (V IN ? I IN ) = cal-
culated nonpositioned power output divided by the
measured voltage-positioned power input.
5) Plot the efficiency data point at the nonpositioned
I LOAD
Figure 8. Transient Response Regions
current, I NP .
The effective efficiency of voltage-positioned circuits is
shown in the Typical Operating Characteristics .
One-Stage (Battery Input) Versus
Two-Stage (5V Input) Applications
The MAX1887/MAX1897 can be used with a direct bat-
tery connection (one stage) or can obtain power from a
regulated 5V supply (two-stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. Due to the high input volt-
age, the one-stage approach requires lower DC input
currents, reducing input connection/bus requirements
and power dissipation due to input resistance. The
transient response of the single stage is better due to
the ability to ramp the inductor current faster. The total
efficiency of a single stage is better than the two-stage
approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I 2 R losses from PC
board traces. Although the two-stage design has slow-
er transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
26
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