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| 型号： | MAX1897ETP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 23/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-TQFN |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
f ESR ≤ SW
In non-CPU applications, the output capacitor selection
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor ’ s ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For out-of-
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
f
π
phase operation, the maximum ESR to meet ripple
requirements is:
where:
f ESR =
1
2 π R ESR C OUT
? ? ( η ? 1 ) V OUT t TRIG ?
? η ? ? ? V IN ? η V OUT ? ? V OUT ? ?
? ? V
? L ? ? ? ?
? ? ? ?
? ?
R ESR ≤
V RIPPLE
f SW ? ? IN ?
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
R ESR ≤
? I LOAD ( MAX ) LIR ? η ( η ? 1 ) ? ?
? ( t ON TRIG ) ?
+ t
?
?
This equation may be rewritten as the single phase rip-
ple current minus a correction due to the additional
phases:
V RIPPLE
? ? V OUT ? ?
L ?
where t TRIG is the MAX1887/MAX1897 ’ s trigger propa-
gation delay, η is the number of phases, and K is from
Table 3. When operating the MAX1897 in-phase (POL
= GND), the high-side MOSFETs turn on together, so
the output capacitors must simultaneously support the
combined inductor ripple currents of each phase. For
in-phase operation, the maximum ESR to meet ripple
requirements is:
capacitors in wide-spread use at the time of publication
have typical ESR zero frequencies below 30kHz. In the
standard application used for inductor selection, the
ESR needed to support a 30mV P-P ripple is 30mV/(40A
x 0.3) = 2.5m ? . Eight 270μF/2V Panasonic SP capaci-
tors in parallel provide 1.9m ? (max) ESR. Their typical
combined ESR results in a zero at 39kHz.
Don ’ t put high-value ceramic capacitors directly across
the output without taking precautions to ensure stability.
Ceramic capacitors have a high ESR zero frequency
and may cause erratic, unstable operation. However,
it ’ s easy to add enough series resistance by placing
the capacitors a couple of centimeters downstream
from the junction of the inductor and FB pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double-pulsing occurs due to noise on
? ( V IN ? V OUT )
R ESR ≤
V RIPPLE
I LOAD ( MAX ) LIR
=
V RIPPLE
? η ? ? V OUT ?
? ? ?
? f SW L ? ? V IN ?
the output or because the ESR is so low that there isn ’ t
enough voltage ramp in the output voltage signal. This
“ fools ” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent V SAG
and V SOAR from causing problems during load tran-
sients. Generally, once enough capacitance is added to
meet the overshoot requirement, undershoot at the ris-
ing load edge is no longer a problem (see the V SAG and
V SOAR equations in the Transient Response section).
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the switching waveforms (V LX and/or I INDUCTOR ). Don ’ t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
______________________________________________________________________________________
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