参数资料
型号: MAX1897ETP+T
厂商: Maxim Integrated Products
文件页数: 21/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-TQFN
标准包装: 2,500
系列: Quick-PWM™
PWM 型: 控制器
输出数: 1
频率 - 最大: 550kHz
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 20-WQFN 裸露焊盘
包装: 带卷 (TR)
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
current-limit threshold of 40mV to 150mV. Use 1% toler-
ance resistors in the divider with 10μA to 20μA DC bias
current to prevent significant errors due to the ILIM
pin ’ s input current. Reducing the current-limit threshold
voltage lowers the sense resistor ’ s power dissipation,
but this also increases the relative measurement error:
2) Determine the master ’ s current-limit threshold from
the valley current limit and low-side MOSFETs ’ max-
imum on-resistance over temperature:
V ITH(MASTER) ≥ 21.8A ? 6m ? = 130mV
Now select the resistive-divider values (R A and R B
V ILIM ( SLAVE )
20 μ A
≤ R D ≤
V ILIM ( SLAVE )
10 μ A
in Figure 5) to set the appropriate voltage at the
master ’ s ILIM input:
R C = ? ?
? ? 1 ? R D
R B = ?
? = 65 k ? to 130 k ?
? to ?
? ? V REF ( MASTER ) ? ?
? ?
? ? V ILIM ( SLAVE ) ? ?
Now, set the current-limit adjustment ratio (A ADJ =
V ITHM(HIGH) /V ITHM(LOW) ) greater than the maximum to
? 10 x 130 mV ? ? 10 x 130 mV ?
? 20 μ A ? ? 10 μ A ?
Selecting R B = 100k ? ±1% provides the following
value for R A :
R A = ?
? 1 ? x 100 k ? ≈ 54 k ?
minimum on-resistance ratio (A RDS = R DS(ON)(MAX) /
R DS(ON)(MIN) ):
A ADJ ≥ A ROS
?
?
2 V
10 x 130 mV
?
?
1 + ? A B ? ≥
? R // R ?
? R LIMIT ?
R DS ( ON )( MAX )
R DS ( ON )( MIN )
3) Determine the slave ’ s current-limit threshold:
V ITHS ≥ 1 . 5 m ? x ?
+ 6 . 4 A ? ≈ 42 mV
Increasing A ADJ improves the master ’ s current-limit
accuracy but also increases the current limit ’ s noise
? 130mV
? 6 m ?
?
?
( R A B ) R DS ( ON )( MIN )
R D = ?
? = 21 k ? to 42 k ?
? to ?
sensitivity. Therefore, R LIMIT may be selected using the
following equation:
// R
R LIMIT ≤
R DS ( ON )( MAX ) ? R DS ( ON )( MIN )
Finally, verify that the total load on the master ’ s refer-
ence does not exceed 50μA:
Select the resistive-divider values (R C and R D in
Figure 5) to set the appropriate voltage at the
slave ’ s ILIM input:
? 10 x 42 mV ? ? 10 x 42 mV ?
? 20 μ A ? ? 10 μ A ?
Selecting R D = 30.1k ? ±1% provides the following
? V REF ?
? ?
I BIAS ( TOTAL ) = ?
? + ?
R C = ?
? 1 ? x 30 . 1 k ? ≈ 113 k ?
V REF
Current Limit Design Example
?
? R A + ( R B // R LIMIT ) ? ? R C + R D ?
≤ 50 μ A
value for R A :
?
?
2 V
10 x 42 mV
?
?
R LIMIT ≤ ( 53 . 6 k ? // 100 k ? ) x 3 m ? ≈ 35 k ?
1 . 3 V x ( 12 V ? 1 . 3 V )
? I INDUCTOR = = 6 . 4 A
I LIMIT ( VALLEY ) = ?
? ? ? x 6 . 4 A ? = 21 . 8 A
? 54 k ? + ( 100 k ? // 34 . 8 k ? ) ?
? = 36 μ A
?
For the typical application circuit shown in Figure 1: V IN
= 12V, V OUT = 1.3V, f SW = 300kHz, η = 2, I LOAD(MAX)
= 50A, L = 0.6μH, R DS(ON)(MAX) = 6m ? , R DS(ON)(MIN )
= 3m ?
1) Determine the peak-to-peak inductor current and
the valley current limit:
12 V x 300 kHz x 0 . 6 μ H
? 50 A ? ? 1 ?
? 2 ? ? 2 ?
4) Determine R LIMIT (Figure 5) from the above equation:
6 m ? ? 3 m ?
5) Finally, verify that that the total bias currents do not
exceed the 50μA maximum load of the master ’ s ref-
erence:
? 2 V ?
I BIAS ( TOTAL ) = ? ?+
? 2 V ?
? 30 . 1 k ? + 113 k ? ?
______________________________________________________________________________________
21
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