参数资料
型号: MAX8792ETD+T
厂商: Maxim Integrated Products
文件页数: 25/28页
文件大小: 0K
描述: IC PWM CTRLR STEP-DWN 14TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
应用: PWM 控制器
输入电压: 2 V ~ 26 V
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 700µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
供应商设备封装: 14-TDFN-EP(3x3)
包装: 标准包装
其它名称: MAX8792ETD+TDKR
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Switching ) = V f
?+
? I GATE ?
rough  estimate  and  is  no  substitute  for  breadboard
evaluation, preferably including verification using a
thermocouple mounted on N H :
? Q G ( SW ) ?
PD ( N H IN ( MAX ) I LOAD SW ?
C OSS V IN 2 f SW
2
where C OSS is the N H MOSFET’s output capacitance,
Q G(SW) is the charge needed to turn on the N H MOS-
Boost Capacitors
The boost capacitors (C BST ) must be selected large
enough to handle the gate charging requirements of
the high-side MOSFETs. Typically, 0.1 μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side, MOSFETs require
boost capacitors larger than 0.1μF. For these applica-
tions, select the boost capacitors to avoid discharging
the capacitor more than 200mV while charging the
high-side MOSFETs’ gates:
FET, and I GATE is the peak gate-drive source/sink cur-
rent (2.2A typ).
Switching losses in the high-side MOSFET can become
C BST =
N × Q GATE
200 mV
? ? ( I LOAD ) R DS ( ON )
? V IN ( MAX ) ? ? ?
PD ( N L Re sistive ) = ? 1 ? ?
C BST =
= 0 . 24 μ F
I LOAD VALLEY ( MAX ) +
= I
= I VALLEY ( MAX ) + ?
?
?
?
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x V IN 2 x f SW switching-loss equation. If the high-side
MOSFET chosen for adequate R DS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N L ), the worst-case power
dissipation always occurs at maximum input voltage:
? ? V OUT ? ? 2
? ?
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I LOAD(MAX) , but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
Δ I L
2
? I LOAD ( MAX ) LIR ?
2
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D L ) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.
where N is the number of high-side MOSFETs used for
one regulator, and Q GATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V GS = 5V). Using the above equation, the required
boost capacitance would be:
2 × 24nC
200 mV
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
Minimum Input-Voltage Requirements
and Dropout Performance
The output voltage-adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time settings. When
working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the on-times. This
error is greater at higher frequencies. Also, keep in
mind that transient response performance of buck reg-
ulators operated too close to dropout is poor, and bulk
output capacitance must often be added (see the V SAG
equation in the Quick-PWM Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time ( Δ I DOWN )
as much as it ramps up during the on-time ( Δ I UP ). The
ratio h = Δ I UP / Δ I DOWN is an indicator of the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V SAG greatly increases
unless additional output capacitance is used.
______________________________________________________________________________________
25
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