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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 10/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
19
MB86860 SPARClite
Table 3-9 Precharge Control
Table3-10 SDRAM Parity Control
Table 3-11 SDRAM Parity
Enable
Table 3-12 SDRAM Enable
SE
SDRAM Enable
0
Disable
1
Enable
3.11. ART : Auto Refresh Timer Register
SDRAM refresh spaces are decided by the values written to auto refresh timers. Clock input is the same as the BIU unit
clock. (CLKIN X frequency multiplier setting)
31
16
15
0
Reserved
TC
Address: 0x80000808 (ASI=0x4)
Reset State: 0x0000FFFF
Figure 3-13 ART Register
bit31-16:
Reserved
bit15-0:
Timer count [TC]
3.12. SSR : SDRAM Status Register
Shows the status of the SDRAM I/F Unit. Access to this register is read only. Writes are invalid. All bit settings are done
automatically by the hardware. When parity errors occur in SDRAM data reads, the value “1” is set to the PER bit.
The PER bit is reset (set to “0”) during read access to this register. The SDI bit value is preserved.
31
5
4
3
1
0
Reserved
PER
Reserved
SDI
Address: 0x80000810 (ASI=0x4)
Reset State: 0x00000000
Figure 3-14 SSR
bit31-5:
Reserved
bit4:
Parity Error Flag [PER]
bit3-1:
Reserved
bit0:
SDRAM Initial Wait Indicator
Table 3-13 Parity Error
Table 3-14 SDRAM Initial Wait Indicator
PER
Parity Error
SDI
SDRAM Initial Wait
Indicator
0
No Error
0
In initial process
1
Parity Error
1
Initialization finished
SPC
SDRAM Parity Control
0
Odd Parity
1
Even Parity
PRC
Precharge
Control
0
All banks
1
Each bank
SPE
SDRAM Parity Enable
0
Disable
1
Enable
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