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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 5/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
14
MB86860 SPARClite
3. Register Maps
Access to registers should be as word data.
3.1. BCR: Buffer Control Register
WDDP sets the number of columns (depth) of write buffers. MCE enables Merge and Collapse. All buffers are
cleared by writing 1 to ICL and RCL. Upon completion of a clear operation, they return to 0. Write buffers have
no bit for clears. IR, RE and WE enable all buffer operations.
31
6
5
4
3
2
1
0
Reserved
MC
E
ICL RCL
IE
RE WE
Address: 0x80000000 (ASI=0x4)
Reset State: 0x00000000
Figure 3-1 BCR Register
bit31-6:
Reserved
bit8-6:
Write Buffer Depth [WBDP]
bit5:
Merge & Collapse Enable [MCE]
bit4:
Instruction Buffer Clear [ICL]
bit3:
Read Buffer Clear [RCL]
bit2:
Instruction Buffer Enable [IE]
bit1:
Read Buffer Enable [RE]
bit0:
Write Buffer Enable [WE]
Table 3-2 Buffer Clear
Table 3-1
MCE
Merge & Collapse
0
Merge & Collapse Collapse is disabled
1
Merge & Collapse is enabled
Table 3-3 Buffer Enable
IE
Instruction
Buffer Enable
RE
Read Buffer
Enable
WE
Write Buffer
Enable
0
Disable
0
Disable
0
Disable
1
Enable
1
Enable
1
Enable
3.2. ARSR : Address Range Specifier Register
This register is for setting SPARClite bus address ranges from CS0# To CS5#.
Start addresses of address ranges
are set in this register. Bits which do not make address comparisons are set in the AMR register. If N bit is 1, its
range is set as a non-cache area. ARSR0-5 set SPARClite bus areas. BW decides SPARClite area bus widths
specified in CS#1~CS#5. CS0# is for ROM area exclusive use. The start address of CS0# is 0. ARSR and CS#
correspond as shown below. CS area settings must not overlap. CS1#~CS5# are not asserted unless both their
ARSR and AMR corresponding areas are set (CS# is not asserted when only ARSR or AMR is set).
ARSR0 (0x80000100)
for setting SPARC area
CS0# (0x80080000 on reset)
ARSR1 (0x80000108)
for setting SPARC area
CS1# (Undefined on reset)
ARSR2 (0x80000110)
for setting SPARC area
CS2# (Undefined on reset)
ARSR3 (0x80000118)
for setting SPARC area
CS3# (Undefined on reset)
ARSR4 (0x80000120)
for setting SPARC area
CS4# (Undefined on reset)
ARSR5 (0x80000128)
for setting SPARC area
CS5# (Undefined on reset)
ICL
Instruction
buffer clear
RCL
Read Buffer
Clear
0
No operation
0
No operation
1
Buffer Clear
1
Buffer Clear
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相关代理商/技术参数 |
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| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
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