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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 8/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
17
MB86860 SPARClite
Note: When [WE] is “0”, READY# input from c w exterior is always valid.
count1
[CN1]
Specifies the number of waits for the first cycle of non-burst and burst
transfers. The number of waits is the value specified for this field + 1,
These bits are valid when [WE] is “1”.
count2
[CN2]
Specifies the number of waits for the 2nd cycle of burst transfers and
thereafter.
Thus when 0 is specified, it is 1 wait. These bits are valid
when [WE] is “1”.
single cycle
burst mode
[SCB]
If this bit is set to “1”, transfers from the 2nd cycle on of a burst transfer
are performed with 0wait.
This bit is valid when set to “1”. Thus this bit
should be set together with [WE].
parity enable
[PE]
Enables and disables Parity functions for access to the corresponding
CS# areas.
Note: When READY# returns in the same cycle as AS#, 0wait is set and when READY# returns in the next
cycle 1wait is set.
3.7. MXPEF : MEXC Parity Error Flag Register
Flags are set when a MEXC or parity error occurs during reads and writes. To clear a Flag, write “0” or perform a
reset.
31
7
6
5
4
3
2
1
0
Reserved
DMXRE
DMXWE
DPRE
Reserved
MXRE
MXWE
PRE
Address: 0x80000430 (ASI=04)
Reset State: 0x00000000
Figure 3-7 MXPEF Register
bit31-7:
Reserved
bit6:
DMA MEXC Read Error [DMXRE]
bit5:
DMA MEXC Write Error [DMXWE]
bit4:
DMA Parity Read Error [DPRE]
bit3:
Reserved
bit2:
CPU MEXC Read Error [MXRE]
bit1:
CPU MEXC Write Error [MXWE]
bit0:
CPU Parity Read Error [PRE]
3.8. MXPECR : MEXC Parity Error Control Register
Performs Return Mode Enable/Disable settings and Parity Check Odd/Even settings during the next Data Read from
the CPU when MEXC flags are set during data writes.
31
2
1
0
Reserved
PAR
MXWEE
Address: 0x80000438 (ASI=04)
Reset State: 0x00000000
Figure 3-10 MXPECR Register
bit31-2:
Reserved
bit1:
Parity bit (Odd Priority=0, Even Priority=1) [PAR]
bit2:
MEXC Write Error Enable [MXWEE]
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