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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 11/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
20
MB86860 SPARClite
3.13. DMCR[0:1] : DMA Control Register
The DMA Control Register performs all DMA operating mode settings and start/stop controls. Whether a source
address range is SDRAM or a SPARClite bus is specified by the SBSn bit. The SIOn bit indicates that a source address
range is I/O. When an SIOn bit is set to “1” (when the source address is an I/O area), the address becomes fixed and is
not incremented. The SCSNn bit specifies in which CS range a source address is located. The SBWn bit specifies
source data bus width. The DBSn bit specifies whether a destination address range is SDRAM or SPARClite. The
DCSn bit specifies in which CS range a destination address is located. The DBWn bit specifies destination data bus
widths. The TCn bit controls EOP signals. If this bit is set to “1”, EOP signals are output upon completion of transfers.
The SBn bit controls DMA operations. If “1” is set to this bit, DMA operation starts. Even if an SB bit is set in the
same channel during a DMA operation, the DMA operation is not affected. Also, if an SB bit I set in another channel
during a DMA operation in one direction, a DMA transfer in the other direction is activated after the DMA transfer in
progress has ended. SIOn, SCSn and SDSn bits become valid when the SBSn bit is set.
Likewise, DCSNn and DDSn
bits become valid when the DBSn bit is set. If the SB0 bit is cleared to “0” during a DMA transfer, the DMA is aborted
and the ABTn bit is set. If a parity error or MEXC is detected during a DMA transfer, DMA stops, and the ERRn bit is
set. All DMACR bit settings and operations should be performed at the same time.
31
30
29
28
26
25
24
23
22
21
20
18
17 16
15
9
8
7
6
5
1
0
SBS0 R SIO0 SCSN0 SBW0 DBS
0
R DIO0 DCSN0 DBW0 reserved TC0 ERR0 ABT0 reserved SB
0
Address: .0x80000C00 (ASI=0x4)
Reset State: 0x00000000
Figure 3-15 DMCR0 Register
31
30
29
28
26
25
24
23
22
21
20
18
17 16
15
9
8
7
6
5
1
0
SBS1 R SIO1 SCSN1 SBW1 DBS
1
R DIO1 DCSN1 DBW1 reserved TC1 ERR1 ABT1 reserved SB
1
Address: .0x80000C00 (ASI=0x4)
Reset State: 0x00000000
Figure 3-16 DMCR1 Register
bit31:
Source Bus Select [SBS]
bit30:
Reserved
bit29:
Source I/O Select [SIO]
bit28-26:
Source CS Number [SCSN]
bit25-24:
Source Bus Width [SBW]
bit23:
Destination Bus Select [DBS]
bit22:
Reserved
bit21:
Destination I/O Select [DIO]
bit20-18:
Destination CS Number [DCSN]
bit17-16:
Destination Bus Width [DBW]
bit15-9:
Reserved
bit8:
Transfer Complete Out [TC]
bit7:
Error [ERR]
bit6:
Abort [ABT]
bit5-1:
Reserved
bit0:
Start Bit [SB]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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