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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 15/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
23
MB86860 SPARClite
4.
CPU Core
4.1. Overview
The SS200 is a High-end embedded SPARC core developed for installation with the ROSS Technology Company
hyperSPARC (RT6xx) as a base. The SS200 Core consists of an IU Part having 2-issue superscalar architecture, a
16KB/4-way instruction cache, a write-through system 16KB/4-way data cache and a IMB (Intra-Module Bus) Bus
Interface which is the internal bus of the SS200 chip. The SS200 Core conforms to SPARC V8 architecture. Instruction
types, execution cycle numbers and comparisons with the old SPARClite core are shown separately. The SS200 Core
simultaneously fetches two 32-bit instructions using a 64-bit instruction bus and simultaneously executes 2 instructions
using 2 ALUs. (Instructions which can be simultaneously executed are partially restricted).
Internal caches control both instructions and data using 16KB/4-way with 64 bits as 1 unit. Data caches are write-
through systems. The SS200 is connected to external modules by IMB buses. IMB buses have a 32-bit address bus, a
64-bit data bus and bus control signals. Because of the internal buses, SS200 external pins have no IMB buses. IMB
bus data buses support Bi-endian. Little-endian data can be directly accessed using Core register settings. The SS200
Core operates at a clock of 2 X the IMB bus interface. It operates at a maximum of 200mhz.
4.2. Power Down Mode
The SS200 can be set to any of 4 modes- Cache OFF Mode, Normal Mode, Sleep Mode and Stop Mode. In Sleep Mode,
since the PLL is operating, a return to normal mode can be made by the external pins. In Stop Mode, however, the PLL
is also stopped, and a reset is therefore required for a return to Normal Mode.
4.3. Debug Support Function
The SS200 supports a break function, address trace buffer and step operation function as debug functions. Selection of
Debug Mode and Normal mode is performed in accordance with external pin status on reset. 3 types of break function
are supported: external pin breaks, address conveyor breaks and software breaks. Address trace buffers store program
count values immediately preceding breaks in 16 columns. By reading this register after breaks, operation immediately
preceding a break can be confirmed. Traps can be made to occur in 1-step units by setting internal register step
execution flags.
4.4. Non-cache
Data handled as Non-cache by the SS200 is area access specified as Non-cache by the ARSR and AMR registers.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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