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参数资料
| 型号： | MB86860 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 6/70页 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
15
MB86860 SPARClite
31
30
29
28
22
21
16
15
0
N
BW
Reserved
ASI<5:0>
Address<31:16>
Address: 0x80000100 (ASI=0x4)-0x8000128
Reset State: Undefined (ARSR0=0x80080000)
Figure 3-2 ARSR Register
bit31:
Non-cache [N]
bit30-29: Bus width [BW] (Reserved for CS#0)
bit29-22: Reserved
bit21-16: ASI<5:0> (Reserved for CS#0)
bit15-0:
Address<31:16> (Reserved for CS#0)
3.3. SDARS : SDRAM Address Range Specifier Register
This register is for setting SDRAM bus areas. Address ranges of starting addresses are set in this register. Bits
which do not make address comparisons are set in the SDAM Register. When N bit is 1, its range is set as a non-
cache area. All area settings must be set so as not to overlap. (CS0#~CS5# areas must also be set so as not to
overlap).
SDARS0 (0x80000130)
for setting SDRAM area
no corresponding CS# (Undefined on reset)
SDARS1 (0x80000138)
for setting SDRAM area
no corresponding CS# (Undefined on reset)
31
30
22
21
16
15
0
N
Reserved
ASI<5:0>
Address<31:16>
Address: 0x80000130 (ASI=0x4)-0x8000138
Reset State: Undefined
Figure 3-3 SDARS Register
bit31:
Non-cache [N]
bit30-22: Reserved
bit21-16: ASI<5:0>
bit15-0:
Address<31:16>
3.4. AMR : Address Mask Register
This is the register for setting CS0#~CS5# address ranges. It sets address ranges in combination with the ARSR
Register. Bits which are set 1 in the AMR Register do not compare addresses with the ARSR Register. Only AMR
Register bits set to 0 compare memory addresses with the ARSR Register and assert CS# if they agree. AMR and
CS# correspond as follows:
AMR0 (0x80000200)
for setting SPARC area
CS0#
(ROM area exclusive use. 0x00030001 on reset)
AMR1 (0x80000208)
for setting SPARC area
CS1#
(Undefined on reset)
AMR2 (0x80000210)
for setting SPARC area
CS2#
(Undefined on reset)
AMR3 (0x80000218)
for setting SPARC area
CS3#
(Undefined on reset)
AMR4 (0x80000220)
for setting SPARC area
CS4#
(Undefined on reset)
AMR5 (0x80000228)
for setting SPARC area
CS5#
(Undefined on reset)
31
22
21
16
15
0
Reserved
ASI mask<5:0>
Address mask<31:16>
Address: 0x80000200 (ASI=0x4)-0x8000228
Reset State: Undefined (AMR0=0x00030001)
Figure 3-4 AMR Register
bit31-22: Reserved
bit21-16: ASI<5:0>
bit15-0:
Address<31:16>
BW
Bus width
00
64 bit
01
32 bit
10
16 bit
11
8 bit
Table 3-4 Bus
width
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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