参数资料
型号: MC33984BPNAR2
厂商: Freescale Semiconductor
文件页数: 25/39页
文件大小: 0K
描述: IC SWITCH HI SIDE DUAL 16-PQFN
标准包装: 1,200
类型: 高端
输入类型: SPI
输出数: 2
导通状态电阻: 4 毫欧
电源电压: 6 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-PowerDFN
供应商设备封装: 16-PQFN(12x12)
包装: 带卷 (TR)
CS
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
C S B
SCLK K
SI
S I
S SO
D 7
O D 7
D 6
O D 6
D 5
O D 5
D 2
O D 2
D 1
O D 1
D 0
O D 0
D 7 *
D 7
D 6 *
D 6
D 5 *
D 5
D 2 *
D 2
D 1 *
D 1
D 0 *
D 0
Notes 1. 1 2 RST R R D S is S 0 , T T a D B Logic , a [1] . . . , a g state D s t during u t e r the t h t above o s t v operation. o i t o r d e r e d e n t r y o f d a t a i n t o t h e S P S S
2. 3 4 D7:D0 0 0 relate 1 1 , , to O O the , , most n d d recent r r ordered n t t h entry r i e f i r s t of 8 t s 8 data t i s o into r o r d the e r e r e d device. t l a n d s t a t u s d a t a o u t o f t h e S P S S e .
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the F I G U R E 4 b . M U L T I P L E 8 b i t W O R D S P I C O M M U N I C A T I O N
N O T E S : . is in lo ic 1 a t e d in g h e a b e o p e r a n .
. 1 , D 2 n d 7 r e la t o e m o r e c e n t
. O D , O D D 2 . . ., a n O D 7 e la t e t o e f b it s f o e f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic
. O D , O D D 2 ..., a O D 7 e p r e s e th b o f d d fa u
first 8 bits of ordered fault and status data out of the device.
Figure 10. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit
messages. A message is transmitted by the MCU starting
Table 10. Serial Input Address and Configuration Bit
Map
with the MSB, D7, and ending with the LSB, D0 ( Table 9 ).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB (D7)
is the watchdog bit and in some cases a register address bit
SI
Registe
r
D
7
D
6
D
5
D
4
Serial Input Data
D3 D2
D1
D0
common to both outputs or specific to an output; the next
three bits, D6 : D4, are used to select the command register;
STATR
s
0
0
0
0
SOA2
SOA1
SOA0
and the remaining four bits, D3 : D0, are used to configure and
OCR
x
0
0
1
CSNS1
IN1_SPI CSNS0 IN0_SP
control the outputs and their protection features.
EN
EN
I
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
SOCHL
R
s
0
1
0
SOCHs SOCL2s SOCL1
s
SOCL0
s
messages are all multiples of eight bits. Any attempt made to
CDTOL
s
0
1
1
OL_DIS CD_DIS
OCLT1
OCLT0
latch in a message that is not eight bits will be ignored.
R
s
s
s
s
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 10 , summarizes the SI registers. The registers are
addressed via D6 : D4 of the incoming SPI word ( Table 9 ).
Table 9. SI Message Bit Assignment
DICR
OSDR
WDR
s
0
1
1
1
1
0
0
0
0
1
1
FAST
SR s
0
0
CSNS
high s
OSD2
0
IN DIS
s
OSD1
WD1
A/Os
OSD0
WD0
Bit
Sig
SI Msg Bit
Message Bit Description
NAR
UOVR
0
1
1
1
1
1
0
0
0
0
0
0
0
UV_dis
0
OV_dis
MSB
D7
Register address bit for output selection.
Also used for watchdog: toggled to satisfy
TEST
x
1
1
1
Freescale Internal Use (Test)
watchdog requirements.
x = Don’t care. ?
D6 : D4
D3 : D1
Register address bits.
Used to configure the inputs, outputs, and
the device protection features and SO
status content.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =
HS1.
LSB
D0
Used to configure the inputs, outputs, and
the device protection features and SO
status content.
33984
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
25
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