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| 型号： | MC33984BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 29/39页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HI SIDE DUAL 16-PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 2 |
| 导通状态电阻： | 4 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-PowerDFN |
| 供应商设备封装： | 16-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 16. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
x
s
s
0
0
0
0
0
0
1
1
0
1
0
1
s
x
s
s
OTFs
0
0
0
OCHFs
0
1
1
OCLFs
1
0
1
OLFs
CSNS1 EN
SOCHs
OL_DIS s
UVF
IN1_SPI
SOCL2s
CD_DIS s
OVF
CSNS0 EN
SOCL1s
OCLT1s
FAULT
IN0_SPI
SOCL0s
OCLT0s
s
1
0
0
s
1
0
0
FAST SR s CSNS high s
IN DIS s
A/O s
0
1
0
1
x
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
–
1
1
1
1
–
0
0
1
1
–
1
1
0
0
–
FSM_HS0
FSM_HS1
IN1 Pin
–
See Table 1
OSD2
WDTO
IN0 Pin
–
–
OSD1
WD1
FSI Pin
UV_dis
–
OSD0
WD0
WAKE Pin
OV_dis
–
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1. ?
x = Don’t care.
Table 17. Fault Register
Previous Address SOA[2:0] = 101
? SOA3 = 0. The returned data contain the programmed
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
values in the OSDR. Bit OD3 (FSM_HS0) reflects the
s
OTF
OCHF OCLFs
s
OLFs
UVF
OVF
FAULT
state of the output HS0 in the Fail-safe Mode after a
watchdog timeout occurs.
? SOA3 = 1. The returned data contain the programmed
OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
OD6 (OTF) = Over-temperature Flag.
OD5 (OCHFs) = Over-current High Flag. (This fault is latched.)
OD4 (OCLFs) = Over-current Low Flag. (This fault is latched.)
OD3 (OLFs) = Open Load Flag.
OD2 (UVF) = Under-voltage Flag. (This fault is latched or not
latched.)
OD1 (OVF) = Over-voltage Flag.
OD0 (FAULT) = This flag reports a fault and is reset by a read
operation.
FAULT report of any fault on HS0 or HS1
values in the WDR. Bit OD2 (WDTO) reflects the status
of the watchdog circuitry. If WDTO bit is Logic [1], the
watchdog has timed out and the device is in Fail-safe
Mode. If WDTO is Logic [0], the device is in Normal
Mode (assuming the device is powered and not in Sleep
Mode), with the watchdog either enabled or disabled.
Bit OD3 (FSM_HS1) reflects the state of the output HS1
in the Fail-safe Mode after a watchdog timeout occurs.
Previous Address SOA[2:0] = 110
? SOA3 = 0. OD3:OD0 return the state of the IN1, IN0,
FSI, and WAKE pins, respectively ( Table 18 ).
Table 18. Pin Register
Note The FS pin reports a fault. For latched faults, this pin is reset
by a new Switch ON command (via SPI or direct input IN).
OD3
IN1 Pin
OD2
IN0 Pin
OD1
FSI Pin
OD0
WAKE Pin
Previous Address SOA[2:0] = 011
Data returned in bits OD1 and OD0 are current values for
the over-current fault blanking time, illustrated in Table 13 . Bit
OD2 reports if the over-current detection timeout feature is
active. OD3 reports if the open load circuitry is active.
Previous Address SOA[2:0] =100
The returned data contain the programmed values in the
DICR.
? SOA3 = 1. The returned data contain the programmed
values in the UOVR. Bit OD1 reflects the state of the
under-voltage protection and bit OD0 reflects the state
of the over-voltage protection. Refer to Table 16 ).
Previous Address SOA[2:0] =111
Null Data. No previous register Read Back command
received, so bits OD2:OD0 are null, or 000.
33984
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
29
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