参数资料
型号: MC34921AE
厂商: Freescale Semiconductor
文件页数: 23/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 800
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 散装
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Step motor driver C is PWM’d via an input from the digital
subsystem on the CPWMA/CDCPWM terminal. This signal is
approximately 20 kHz to 40 kHz. There are pull-downs on the
PWM input terminals so that DC motor drive C will default to
a safe condition in the event of a connection failure.
GATEOUT
Bit
V b
GATEOUT
R S
B+
STEP MOTOR DRIVER
A step motor driver can be configured as a DC motor driver
(refer to preceding paragraph DC Motor Drivers ) or, when
B+ NOM ≤ 20 V, as a unipolar step driver. Serial input
configuration frame bit 4 determines the mode: 0 = step
mode, 1 = DC mode. A step motor driver will only be used in
B+ = 12 V to 20 V applications.
Note It is possible to use the step motor driver with
B+ > 20 V if the step motor is driven from a separate supply
that is ≤ 20 V.
The step motor driver on the 34921 is a unipolar, voltage-
mode wave drive circuit employing synchronous rectification.
The centertap of each phase-counterphase pair is connected
to B+.
Two PWM signals are sent directly from the digital
subsystem. The CPWMA/CDCPWM terminal provides the
PWM signal for the A and A outputs. The CPWMB terminal
provides the PWM signal for the B and B outputs. The step
motor driver employs synchronous rectification to control
substrate currents. In synchronous rectification, when an
output is turned off, the counterphase output MOSFET is
turned on to maintain current continuity. In order to avoid a
large shoot-through current, there is a dead time delay
(t delay ) between phase off and counterphase on. Refer to
VBOOST CHARGE PUMP
The high-side MOSFETs in the DC motor H-bridges and
the external GATEOUT switch need a gate voltage in excess
of B+, which is provided by the VBOOST supply. The
VBOOST regulator is a charge pump, switching directly off
the B+ supply and operating at 200 kHz.
EXTERNAL N-FET GATE DRIVE OUTPUT
The GATEOUT terminal is an output for a high-side
N-channel MOSFET gate drive. The output will be used to
drive an external high-side MOSFET switch (see figure
below). When enabled, GATEOUT will be connected to the
V b supply. The edge rates when switching the transistors
must be controlled so that shoot-through current does not
affect B+.
C S
Figure 11. External N-FET Gate Drive Circuit
CLOCKING SCHEMES
There are two basic clocking schemes that can be used
while clocking data into the MC34921 IC. One has 16 rising
edges of SCLK while CE is in a logic low state and the other
has 15 rising edges of SCLK. In the 15 SCLK clocking
scheme, the input data and output data are latched on the
same clock edge. In the timing diagram on page 16 , the
numbers on the MOSI line are the bits that will be clocked into
the input shift register at the rising edge of SCLK. They are
drawn occurring before SCLK to account for the required
setup time (minimum 15ns). The numbers on the MISO line
are the bits that will be clocked out at the rising edge of SCLK.
They are drawn occurring after SCLK to account for the
output delay from the rising edge of SCLK (maximum 40ns).
The numbers on the SCLK line are for reference only.
Note: when using the 15 bit clocking method with exactly
one rising edge of SCLK when CE is in a logic high state, the
output data to be sent out is latched at the same time the
IREQ bit is latched in. The next frame following the assertion
of the IREQ bit is the IREQ data. I.e., the frame after the
sending of the IREQ bit will have the data from the IREQ
register rather than skipping one frame. Note: regarding the
reporting of the DONE bit after the completion of an A/D
conversion: the DONE bit is sent out every time a conversion
completes. This requires the user to hold the MOSI pin in a
low state when it is not being used to transmit data. Refer to
SUPERVISORY (RST) FUNCTION
Supervisory Circuitry
The supervisor circuitry provides control of the RST line, an
open drain signal, based on system operating conditions
monitored by the 34921 IC. V 5.0 , V 3.3 , V CORE , B+, and
thermal shutdown detectors in various parts of the chip are
monitored for error conditions. Because other devices in the
system may trigger a reset, the RST line itself is also
monitored, but the supervisor circuitry controls all reset
timing, including externally generated resets. Driving the RST
line low causes the system to be held in the reset state. V 5.0 ,
34921
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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