参数资料
型号: MC34921AE
厂商: Freescale Semiconductor
文件页数: 30/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 800
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 散装
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 15. NORMAL Mode Output Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A/Dd7 A/Dd6 A/Dd5 A/Dd4 A/Dd3 A/Dd2 A/Dd1 A/Dd0
Info
A/Dr2
A/Dr1
A/Dr0 DENCB DENCA A/Ddone2 A/Ddone1
Table 16. NORMAL Mode Output Frame Bit Allocation Model
Bit
15 –8
7
6 –4
3 –2
1 –0
Bit Name
A/Dd[7:0]
Info
A/Dr[2:0]
DENCB,
DENCA
A/Ddone2,
A/Ddone1
Bit Description
ADC data from last conversion.
Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
Report the input to the ADC that is represented in the A/Dd[7:0] (Bits 15 –8).
Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
Flag completion of the ADC for corresponding conversion. If ADC in single conversion mode, only A/Ddone1 is
asserted. If in double conversion mode, A/Ddone1 is asserted for first conversion and A/Ddone2 is asserted for
second conversion
NFO (IREQ) MODE:
NFO (IREQ) Mode is the mode in which the MC34921 IC reports status and error information via the serial interface.
Table 17. NFO (IREQ) Mode Output Frame Programming Model I
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
EXT
B+UV
Info
V5VUV 3.3UV
CoreU
DENC
DENC
TSD
TW
Table 18. INFO (IREQ) Mode Output Frame Bit Allocation
V
B
A
Bit
15 –10
9
8
7
6
5
4
3 –2
1
0
Bit Name
Reserved
EXT
B+UV
Info
V5VUV
3.3UV
CoreUV
DENCB,
DENCA
TSD
TW
Bit Description
These bits will report [011000].
This flag will report if the last generated reset was due to an external signal driving RST.
Undervoltage flag for the B+ input voltage. If the input voltage drops below that necessary for the 34921 to
operate, this flag will be asserted.
Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
Undervoltage warning for the 5.0 V regulator. This will be asserted when a fault on the 5.0 V causes the voltage
to droop.
Undervoltage warning for the 3.3 V regulator. This will be asserted when a fault on the 3.3 V causes the voltage
to droop.
Undervoltage warning for the VCORE linear regulator. This will be asserted when a fault on the VCORE voltage
causes the voltage to droop.
Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
Thermal shutdown flag. This flag will report if the last generated reset was due to a TSD. Thermal shutdown
occurs when the junction temperature reaches approximately 140oC.
Thermal warning flag. This bit is asserted when the junction temperature on the die reaches approximately
110oC.
34921
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
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