参数资料
型号: MC34921AE
厂商: Freescale Semiconductor
文件页数: 26/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 800
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 散装
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
determined by the A/Da[2 : 0] bits in the serial normal input
frame (refer to Table 11 , page 28 ).
Three different types of conversion can occur (refer to
Table 7 ):
? Single Conversion 00X does a single conversion of
inputs AN0/ANALOGOUT_A or AN1/ANALOGOUT_B.
? Double Conversion 1XX does a double conversion of
channels A and B, A and A , B and B , or
AN2/ANALOGIN_A and AN3/ANALOGIN_B,
respectively.
? Auto-Select Conversion 011 does a single
conversion of one of the outputs from the analog
encoder interface, as selected by the digital outputs of
the analog encoder interface, DENCA and DENCB.
Table 7. A/D Input Conversion Channel Addressing
NORMAL
Input
NORMAL
Input
NORMAL
Input
NORMAL
Output
NORMAL
Output
Frame
Bit 2
A/Da0
0
1
1
1
1
1
1
0
0
1
Frame
Bit 3
A/Da1
0
0
1
1
1
1
0
0
1
1
Frame
Bit 4
A/Da2
0
0
0
0
0
0
1
1
1
1
Frame
Bit 2 (27)
DENCA
X
X
1
0
1
0
X
X
X
X
Frame
Bit 3 (27)
DENCB
X
X
0
1
1
0
X
X
X
X
Input(s) Selected
AN0/ANALOGOUT_A terminal
AN1/ANALOGOUT_B terminal
Analog encoder interface output A
Analog encoder interface output A
Analog encoder interface output B
Analog encoder interface output B
Analog encoder interface outputs A and A with S/H (28)
Analog encoder interface outputs A and B with S/H (28)
Analog encoder interface outputs B and B with S/H (28)
AN2/ANALOGIN_A and AN3/ANALOGIN_B terminals (direct input) with
S/H (28)
Notes
Notes
27. DENCA and DENCB values are captured at the output of the 3 or 6 Edge filter on SCLK rising edge, then immediately
shifted out in the MISO data when CE is high.
28. Inputs are listed in order of conversion.
A/D Conversion Flow
There is a START conversion bit in the serial channel. The
presence of this bit begins a conversion cycle on the input(s)
selected in that frame. If the ADC is converting when a
subsequent START bit arrives, this start request will be
ignored. Figure 14, A/D Converter Input Structure , page 27 ,
shows how this process works. The current conversion
completes during the frame prior to the data being returned.
If there is a START bit in that input frame, another conversion
is begun as the previous conversion’s data is being shifted
out. If there is no START bit in the input frame, then another
conversion is begun the frame following receipt of the start
bit. The single conversion rate is paced at four frames for
configuration bit 3 =0 or eight frames (or less) for
configuration bit 3 =1, including sampling time (refer to
Table 13 , CONFIG Input Frame Bit Allocation, page 29 ). In
order to simplify implementation of the 34921, the user must
ensure that no A/D conversions are in progress when an
INFO word is requested. For input pairs, the inputs are listed
in the order of conversion in Table 7 .
34921
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
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