参数资料
型号: MC34921AE
厂商: Freescale Semiconductor
文件页数: 28/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 800
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 散装
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE:
Normal mode is the normal operating mode of the IC (as opposed to the Configuration mode or Information Request mode).
Table 10. NORMAL Mode Input Frame Programming Model
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OUT2
OUT1
B
B
A /Cdcb A/Cdca
Adcb
Adca
Bdcb
Bdca
GATE
A/Da2
A/Da1
A/Da0
start
config
OUT
Table 11. NORMAL Input Frame Bit Allocation (29)
Bit
15 – 14
13 – 10
11 – 10
9– 8
7– 6
5
4 –2
1
0
Bit Name
OUT2, OUT1
B , B, A , A
A /Cdca, A/Cdcb
Adcb, Adca
Bdcb, Bdca
GATEOUT
A/Da[2:0]
start
config
Bit Description
High-side or low-side output control. Bit 4 of the configuration mode input frame determines which output is
controlled. Output turns on when corresponding bit is asserted. Refer to Table 20 and Table 21 Truth Tables,
page 31 and page 32 , respectively, for operation.
Step motor outputs, inverting. Corresponding output on when bit asserted. Refer to Table 22 Truth Table,
page 32 , for operation.
Motor driver C direction bits. Outputs follow these bits, regardless of PWM value, when they are equal; i.e., 00
or 11. Refer to Table 19 Truth Table, page 31 , for operation.
Motor driver A direction bits. Outputs follow these bits, regardless of PWM value, when the are equal; i.e., 00
or 11. Refer to Table 19 Truth Table, page 31 , for operation.
Motor driver B direction bits. Outputs follow these bits, regardless of PWM value, when the are equal; i.e., 00
or 11. Refer to Table 19 Truth Table, page 31 , for operation.
Assertion puts V b on the GATEOUT terminal. Deassertion connects the GATEOUT terminal to ground.
A/D conversion target channel. These bits determine which input(s) to the ADC are to be converted.
A/D conversion start bit. This bit causes the ADC to sample the input(s) specified by bits A/Da[2:0] (bits [4:2])
and begin an analog-to-digital conversion. This bit is ignored if a conversion is already in progress.
The input frame can be either a configuration frame or a normal frame. Bit 0 determines the type of frame being
received. Bit 0 = 0 is a normal mode input frame.
Notes
29. All defaults = 0 at power up.
30. When in DC motor mode.
31. When in step motor mode, outputs are A, A , B, and B ; when in DC motor mode, outputs B and B have no function.
34921
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
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