参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 114/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
Resets
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
79
Preliminary
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
Reset sequencing
Clock control & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detail in the sections that follow.
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