参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 3/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
56F8322 Techncial Data, Rev. 16
100
Freescale Semiconductor
Preliminary
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and
GPIOx_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values of
these registers.
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please
contact
your
Freescale
marketing
representative
or
authorized
distributor
for
device/package-specific BSDL information.
The TRST pin is not available in this package. The pin is tied to VDD in the package.
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the 56F8300 Peripheral User Manual.
GPIOB7
PHASEA0 / TA0
38
Quad Decoder 0 register DECCR is used to select
between Decoder 0 and Timer A
Quad Dec is NOT available in 56F8122
GPIOC0
EXTAL
32
Pull-ups should default to disabled
GPIOC1
XTAL
33
Pull-ups should default to disabled
GPIOC2
CAN_RX
46
CAN is NOT available in 56F8122
GPIOC3
CAN_TX
47
CAN is NOT available in 56F8122
GPIOC4
TC3
GPIOC5
TC1 / RXD0
48
SIM register SIM_GPS is used to select between Timer C
and SCI0 on a pin-by-pin basis
GPIOC6
TC0 / TXD0
1
SIM register SIM_GPS is used to select between Timer C
and SCI0 on a pin-by-pin basis
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8322 / 56F8122
Pins in italics are NOT available in the 56F8122 device
GPIO Function
Peripheral Function
Package Pin
Notes
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