参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 51/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
Signal Pins
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
21
Preliminary
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
38
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PHASEB0
(TA1)
(GPIOB6)
(SYS_CLK2)
37
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel 1
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK2 signal
(see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEB0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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