参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 13/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
Architecture Block Diagram
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
11
Preliminary
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures.
The 56F8322/56F8122 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the
internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the
on-board regulator and power and ground signals. They also do not show the multiplexing between
peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which
signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
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