参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 52/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
56F8322 Techncial Data, Rev. 16
22
Freescale Semiconductor
Preliminary
INDEX0
(TA2)
(GPIOB5)
(SYS_CLK)
36
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Index — Quadrature Decoder 0, INDEX input
TA2 — Timer A, Channel 2
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK signal
(see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is INDEX0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
HOME0
(TA3)
(GPIOB4)
(prescaler_
clock)
35
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal prescaler_clock
signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is HOME0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
SCLK0
(GPIOB3)
19
Schmitt
Input/
Output
Schmitt
Input/
Output
Tri-Input,
pull-up
enabled
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as the
data clock input. A Schmitt trigger input is used for noise immunity.
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SCLK0.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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