参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 115/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
56F8322 Techncial Data, Rev. 16
8
Freescale Semiconductor
Preliminary
1.1.3
Memory
Note: Features in italics are NOT available in the 56F8122 device.
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection
On-chip memory, including a low-cost, high-volume Flash solution
— 32KB of Program Flash
— 4KB of Program RAM
8KB of Data Flash
8KB of Data RAM
8KB of Boot Flash
EEPROM emulation capability
1.1.4
Peripheral Circuits
Note: Features in italics are NOT available in the 56F8122 device.
One Pulse Width Modulator module with six PWM outputs and one Fault input; fault-tolerant design with
dead time insertion; supports both center-aligned and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual,
3-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, Channel 2
Temperature Sensor is tied internally to analog input (ANA7) to monitor the on-chip temperature
Two 16-bit Quad Timer modules (TMR) totaling six pins:
— In the 56F8322, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction
with the PWMA and ADCA
— In the 56F8122, Timer C works in conjunction with ADCA
One Quadature Decoder which works in conjunction with Quad Timer A
FlexCAN (Can Version 2.0 B-compliant) module with 2-pin port for transmit and receive
Up to
two Serial Communication Interfaces (SCIs)
Up to
two Serial Peripheral Interfaces (SPIs)
Computer Operating Properly (COP)/Watchdog timer
One dedicated external interrupt pin
21 General Purpose I/O (GPIO) pins
Integrated Power-On Reset and Low-Voltage Interrupt Module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
Software-programmable, Phase Lock Loop (PLL)
On-chip relaxation oscillator
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