参数资料
型号: MC56F8122VFAE
厂商: Freescale Semiconductor
文件页数: 117/136页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
Operating Mode Register
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
81
Preliminary
6.4 Operating Mode Register
Figure 6-1 OMR
The reset state for the MB bit will depend on the Flash secured state. See Section 4.2 and Part 7 for
detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device.
The EX bit is not functional in this device since there is no external memory interface. For all other bits,
see the 56F8300 Peripheral User Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
6.5 Register Descriptions
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NL
CM
XP
SD
R
SA
EX
0
MB
MA
Type
R/W
RESET
0
0000
0
X
0
Table 6-1 SIM Registers
(SIM_BASE = $00 F350)
Address Offset
Address Acronym
Register Name
Section Location
Base + $0
SIM_CONTROL
Control Register
Base + $1
SIM_RSTSTS
Reset Status Register
Base + $2
SIM_SCR0
Software Control Register 0
Base + $3
SIM_SCR1
Software Control Register 1
Base + $4
SIM_SCR2
Software Control Register 2
Base + $5
SIM_SCR3
Software Control Register 3
Base + $6
SIM_MSH_ID
Most Significant Half of JTAG ID
Base + $7
SIM_LSH_ID
Least Significant Half of JTAG ID
Base + $8
SIM_PUDR
Pull-up Disable Register
Reserved
Base + $A
SIM_CLKOSR
CLKO Select Register
Base + $B
SIM_GPS
GPIO Peripheral Select Register
Base + $C
SIM_PCE
Peripheral Clock Enable Register
Base + $D
SIM_ISALH
I/O Short Address Location High Register
Base + $E
SIM_ISALL
I/O Short Address Location Low Register
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