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参数资料
| 型号： | MC68CK338CPV14B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, TQFP-144 |
| 文件页数： | 102/133页 |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MOTOROLA
MC68CK338
70
MC68CK338TS/D
CPTQP[3:0] — Completed Queue Pointer
CPTQP[3:0] points to the last command executed. It is updated when the current command is complete.
When the first command in a queue is executing, CPTQP[3:0] contains either the reset value ($0) or a
pointer to the last command completed in the previous queue.
5.5.3 QSPI RAM
The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the
CPU. The RAM is divided into three segments: receive data, transmit data, and command control data.
Receive data is information received from a serial device external to the MCU. Transmit data is infor-
mation stored by the CPU for transmission to an external peripheral. Command control data is used to
perform the transfer.
Figure 16 displays the organization of the RAM.
Figure 16 QSPI RAM
Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate
independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating
that it is finished, and then either interrupts the CPU or waits for CPU intervention. It is possible to ex-
ecute a queue of commands repeatedly without CPU intervention.
RR[0:F] — Receive Data RAM
$YFFD00
Data received by the QSPI is stored in this segment. The CPU reads this segment to retrieve data from
the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to
zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using
byte, word, or long-word addressing.
The CPTQP[3:0] value in SPSR shows which queue entries have been executed. The CPU uses this
information to determine which locations in receive RAM contain valid data before reading them.
TR[0:F] — Transmit Data RAM
$YFFD20
Data that is to be transmitted by the QSPI is stored in this segment. The CPU usually writes one word
of data into this segment for each queue command to be executed.
QSPI RAM MAP
RECEIVE
RAM
TRANSMIT
RAM
500
51E
520
53E
WORD
540
54F
COMMAND
RAM
BYTE
WORD
RR0
RR1
RR2
RRD
RRE
RRF
TR0
TR1
TR2
TRD
TRE
TRF
CR0
CR1
CR2
CRD
CRE
CRF
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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