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| 型号： | MC68CK338CPV14B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, TQFP-144 |
| 文件页数： | 12/133页 |
| 文件大小： | 944K |
| 代理商： | MC68CK338CPV14B1 |
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MC68CK338
MOTOROLA
MC68CK338TS/D
109
RTCSM registers are write protected in standby mode to prevent loss of data in runaway situations. For
the same reason, the RAMSMs are also write protected in standby mode.
If the standby mode function is not required in a given application, VRTC should be powered from the
VDD and VDDSYN supply. Unpredictable operation of the RAMSMs and RTCSM may result otherwise.
6.15 CTM6 Interrupts
The CTM6 is able to request numerous interrupts on the IMB. Each submodule that is able to request
interrupts can do so with any of seven levels. Each submodule that is able to request interrupts includes
a 3-bit level number and a 1-bit arbitration number that is initialized by software.
The 3-bit level number selects which of seven interrupt signals on the IMB are driven by that submodule
to create an interrupt request. Of the four priority bits provided on the IMB during arbitration among the
modules, one of them comes from the chosen submodule, and the BIUSM provides the other three.
Thus, the CTM6 responds to two of the possible 15 arbitration numbers.
During the IMB arbitration process, the BIUSM manages the separate arbitration among the CTM6 sub-
modules to determine which submodule should respond. Of the submodules which have an interrupt
request pending at the level being arbitrated on the IMB, the submodule which has the lowest address
is given the highest priority to respond.
When the IARB number is not unique for a given module, simultaneous interrupts are prioritized in hard-
ware according to the vector number or the submodule interrupt arbitration sequence number shown in
Table 66. Following the interrupt arbitration process, the CTM6 provides an 8-bit vector number. Six of
the eight bits are provided by the submodules. A submodule can identify two separate interrupt sources
with unique interrupt vectors. The two high-order bits of the 8-bit vector are provided by the BIUSM. The
six low-order vector bits identify the highest priority interrupt request pending in the CTM6 at the begin-
ning of the arbitration cycle.
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