参数资料
型号: MC68CK338CPV14B1
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封装: PLASTIC, TQFP-144
文件页数: 59/133页
文件大小: 944K
代理商: MC68CK338CPV14B1
MC68CK338
MOTOROLA
MC68CK338TS/D
31
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. If a chip-select function is given the same address as a microcontroller module or
an internal memory array, an access to that address goes to the module or array, and the chip-select
signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits except CSBOOT are disabled out of reset. Chip-select option registers must not
be written until base addresses have been written to the proper base address registers. Alternate func-
tions for chip-select pins are enabled if appropriate data bus pins are held low at the release of RESET.
Table 17 lists allocation of chip-selects and discrete outputs on the pins of the MCU.
3.6.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment registers CSPAR[0:1]
determine functions of the pins. Pin assignment registers also determine port size for dynamic bus al-
location. A pin data register (PORTC) latches data for chip-select pins that are used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two Kbytes to one Mbyte
can be selected by writing values to the appropriate base address registers CSBARBT and CS-
BAR[0:10]. Multiple chip-selects assigned to the same block of addresses must have the same number
of wait states.
Chip-select option registers CSORBT and CSOR[0:10] determine timing of and conditions for assertion
of chip-select signals. Eight parameters, including operating mode, access size, synchronization, and
wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the chip-select cir-
cuits. CSBOOT and registers CSORBT and CSBARBT are provided to support bootstrap operation.
3.6.2 Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields that determine functions of the chip-select pins.
Each pin has two or three possible functions, as shown in Table 18.
Table 17 Chip-Select and Discrete Output Allocation
Pin
Chip-Select
Discrete Outputs
CSBOOT
BR
CS0
BG
CS1
BGACK
CS2
FC0
CS3
PC0
FC1
CS4
PC1
FC2
CS5
PC2
ADDR19
CS6
PC3
ADDR20
CS7
PC4
ADDR21
CS8
PC5
ADDR22
CS9
PC6
ADDR23
CS10
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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