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参数资料
型号： MC68EN302CPV20BT
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封装： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件页数： 4/128页
文件大小： 641K
代理商： MC68EN302CPV20BT
MC68EN302 Electrical Characteristics
8-2
MC68EN302 REFERENCE MANUAL
MOTOROLA
8.3 DRAM INTERFACE TIMING
Any spec numbers shown in diagrams and not listed in the table are unchanged from the
MC68302 User’s Manual.
NOTES:
1. Width increases by clock period (Tcyc) for each wait state added.
2. Width increases by clock period (Tcyc) for each increase in P1–P0 (RAS precharge time).
3. Parity Enabled timing (spec 27A) only applies to bank(s) which have parity enabled.
Table 8-1. DRAM Interface Timing
NUM
CHARACTERISTIC
SYMBOL
20 MHZ
25 MHZ
UNIT
MIN
MAX
MIN
MAX
6A
CLKO Low to Column Address Valid
0
25
0
25
9
CLKO High to AS, RASx Asserted
3
25
3
20
ns
9A
CLKO High to RASx Deasserted
3
25
3
20
ns
400
RASx Asserted to Row Address Invalid
12
-
12
-
ns
401
RASx Asserted to Column Address Valid
15
-
15
-
ns
402
RASx Width Asserted (1)
85
-
75
-
ns
403
RASx Width Negated (2)
85
-
75
-
ns
404
RASx Asserted to CAS Asserted
35
-
35
-
ns
405
CLKO High to CASx Asserted
3
25
3
20
ns
405A
CLKO High to CASx Asserted (Refresh)
3
25
3
20
ns
406
CLKO High to CASx Negated
3
25
3
20
ns
407
Column Address Valid to CASx Asserted
15
-
15
-
ns
408
CASx Asserted to Column Address Negated
50
-
40
-
ns
409
CASx Asserted to RASx Negated
35
-
30
-
ns
410
CASx Width Asserted (1)
75
-
60
-
ns
411
CASx Width Negated (2)
75
-
60
-
ns
412
CASx Negated to Data, Parity-In invalid
0-0-
ns
415
DRAMRW Low to CASx Asserted
30
-
25
-
ns
416
CASx Asserted to DRAMRW High
100
-
80
-
ns
417
Data-Out Valid to CASx Asserted
15
-
10
-
ns
417A
Parity-Out Valid to CASx Asserted
0-0-
ns
418
CAS asserted to Data/Parity-Out Invalid (1)
100
-
80
-
ns
419
CLKO Low to AMUX Negated
3
15
3
15
ns
420
CLKO Low to AMUX Asserted
3
15
3
15
ns
421
AMUX High to RASx Asserted
50
-
40
-
ns
422
RASx Asserted to AMUX Low
10
-
10
-
ns
423
AMUX Low to CAS Asserted
15
-
15
-
ns
424
CASx Asserted to AMUX High
55
-
45
-
ns
23
CLKO Low to Data Out Valid
-
25
-
20
ns
23A
CLKO Low to Parity Out Valid
-
40
-
33
ns
27
Data-In to CLKO Low (Parity Disabled) (3)
6-5-
ns
27A
Data/Parity-In to CLKO Low (Parity Enabled) (3)
16
-
12
-
ns
425
CLKO High to PARITYE Valid
-
15
-
15
ns
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