- 您现在的位置：买卖IC网 > PDF目录45215 > MC68EN302CPV20BT (FREESCALE SEMICONDUCTOR INC) 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 PDF资料下载
参数资料
| 型号： | MC68EN302CPV20BT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件页数： | 84/128页 |
| 文件大小： | 641K |
| 代理商： | MC68EN302CPV20BT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页当前第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
ETHERNET Controller
4-20
MC68EN302 REFERENCE MANUAL
MOTOROLA
The transmit FIFO control logic provides a signal indicating data is available to the Ethernet
transmit protocol machine. If underflow occurs, the Ethernet transmit protocol machine will
handle aborting the frame (append a bad CRC) and flushing the remainder of the frame from
the FIFO.
If a collision occurs within the slot time in a transmit frame, the FIFO supports retry by
maintaining a separate start of frame pointer (read lag pointer). New data is never written on
top of start of frame data until the slot time has passed. Two control signals pass between
the Ethernet transmit logic and the transmit FIFO to indicate when the slot time (collision
window) has been passed (Transmit Accept) or when a collision retry must take place
(Transmit Retry).
4.4.2 RECEIVE FIFO
The receive FIFO control logic provides “data available” and “receive FIFO empty” flow
control signals to the receive DMA controller. The “data available” signal is asserted as a
function of the number of bytes available in the FIFO and the WMRK bits from the EDMA
register. If overflow occurs, the STATUS word will have the OU bit set which will be written
into the receive BD. The frame should be discarded by software.
Data is written into the receive FIFO by the Ethernet receive logic in the case of status
information, and by the address recognition logic if the Reason and ARIndex fields are
enabled.
The receive FIFO control logic maintains a “start of frame” pointer that allows purging
collision fragments from the FIFO so that they need not be DMA’d. This purging of fragments
(runt frames less than 64 bytes long) is automatic and cannot be disabled.
4.5 ETHERNET PROTOCOL LOGIC
This block implements the MAC (media access control) sublayer of the IEEE 802.3
standard, supporting operation up to 10 Mbps compliant with both Ethernet and 802.3
standards. This logic is subdivided into transmit, receive and loopback/serial interface
sections.
4.5.1 ETHERNET TRANSMIT
The Ethernet transmiter block performs the following functions:
Parallel to serial conversion of data
Encapsulation of transmit frames
— Generation of preamble (PA) and start of frame delimiter (SFD)
— Transmits serial data from the transmit FIFO interface
— Pads short frames (with 0’s)
— Appends CRC, if required
— Appends bad CRC if required
— Appends JAM pattern (all 1’s)
Transmit Protocol
相关PDF资料 |
PDF描述 |
|---|---|
| MC68302FC20CR2 | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| MC68302FC16CR2 | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| MC68LC302PU20CT | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| MC68EN302PV25BT | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| MC68302PV33C | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68EN302PV20 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Integrated Multiprotocol Processor with Ethernet |
| MC68EN302PV20BT | 功能描述:IC MPU MULTI-PROTOCOL 144-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| MC68EN302PV25 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Integrated Multiprotocol Processor with Ethernet |
| MC68EN302PV25BT | 功能描述:IC MPU MULTI-PROTOCOL 144-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| MC68EN360AI25L | 功能描述:微处理器 - MPU QUICC ETHRN RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。